TMS320F datasheet(381/389 Pages) TI

381 / 389 page

Index

Index-4

carry bit (C)

(continued)

definition

4-16

involved in accumulator events

4-10

used during ROL and ROR instructions

7-143

to 7-145

CC instruction

7-59

central arithmetic logic section of CPU

4-8

CHAR LEN2–0 bits

5-18, 5-19

character length

5-18, 5-19

CLKOUT1 signal, definition

D-3

CLRC instruction

7-61

CMPL instruction

7-63

CMPR instruction

7-64

CNF (DARAM configuration bit)

3-5, 4-16

codec, definition

D-3

conditional instructions

5-10 to 5-13

conditional branch

5-11 to 5-13

conditional call

5-12 to 5-13

conditional return

5-12 to 5-13

conditions that may be tested

5-10

stabilization of conditions

5-11

using multiple conditions

5-10

configuration

global data memory

3-9

multiprocessor

C-13

program memory

3-5

connector

14-pin header

C-2

dimensions, mechanical

C-14

DuPont

C-2

control bits

CHAR LEN2–0

5-18, 5-19

PARITY ENABLE

5-18

STOP BITS

5-18

CPU

accumulator

4-9

arithmetic logic section

4-8

auxiliary register arithmetic unit (ARAU)

4-12

block diagram (partial)

4-2

CALU (central arithmetic logic unit)

4-9

central arithmetic logic unit (CALU)

4-9

definition

D-4

input scaling section/input shifter

4-3

multiplication section

4-5

output shifter

4-11

overview

2-8

CPU

(continued)

product shifter

4-6

product shift modes

4-7

program control

2-10

status registers ST0 and ST1

4-15

CPU interrupt registers

5-17

current auxiliary register

6-9

add short immediate value to (ADRK

instruction)

7-32

branch if not zero (BANZ instruction)

7-40

compare with AR0 (CMPR instruction)

7-64

increment or decrement (MAR

instruction)

7-110

role in indirect addressing

6-9 to 6-16

subtract short immediate value from (SBRK

instruction)

7-153

update code (ARU)

6-12

D0–D15 (external data bus), definition

D-4

DARAM

2-5

DARAM configuration bit (CNF)

4-16

data memory

3-2

data page pointer (DP)

4-16

global data memory

3-9

local data memory

3-6

off-chip

3-8

on-chip

3-8

on-chip registers

3-7

data page 0

address map

3-7

on-chip registers

3-7

RAM block B2 (scratch-pad RAM)

3-7

data page pointer (DP)

caution about initializing DP

6-5

definition

4-16

load (LDP instruction)

7-82

role in direct addressing

6-4

data read bus (DRDB)

2-4

data write bus (DWEB)

2-4

data-read address bus (DRAB)

2-4

data-scaling shifter

at input of CALU

4-3

at output of CALU

4-11

data-write address bus (DWAB)

2-4

diagnostic applications

C-24

TMS320F Datasheet(PDF) 381 Page - Texas Instruments

TMS320F Datasheet(HTML) 381 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL