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TMS320F Datasheet(PDF) 382 Page - Texas Instruments

Part # TMS320F
Description  CPU and Instruction Set
PDF  389 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320F Datasheet(HTML) 382 Page - Texas Instruments

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Index
Index-5
dimensions
12-pin header
C-20
14-pin header
C-14
mechanical, 14-pin header
C-14
direct addressing
description
6-4
examples
6-6
figure
6-5
opcode format
6-5 to 6-7
role of data page pointer (DP)
6-4
divide (SUBC instruction)
7-179
DMOV instruction
7-65
DP (data page pointer)
caution about initializing DP
6-5
definition
4-16
load (LDP instruction)
7-82
role in direct addressing
6-4
DRAB (data-read address bus)
2-4
DRDB (data read bus)
2-4
DS signal
4-18
dual-access RAM
2-5
dual-access RAM (DARAM)
D-4
DuPont connector
C-2
DWAB (data-write address bus)
2-4
DWEB (data write bus)
2-4
E
EMU0/1
configuration
C-21, C-23, C-24
emulation pins
C-20
IN signals
C-21
rising edge modification
C-22
EMU0/1 signals
C-2, C-3, C-6, C-7, C-13, C-18
emulation
configuring multiple processors
C-13
JTAG cable
C-1
pins
C-20
serial-scan
2-10
timing calculations
C-7 to C-9, C-18 to C-26
using scan path linkers
C-16
emulation timing
C-7
emulator
cable pod
C-5
connection to target system, JTAG mechanical
dimensions
C-14 to C-25
designing the JTAG cable
C-1
emulator
(continued)
emulation pins
C-20
pod interface
C-5
pod timings
C-6
signal buffering
C-10 to C-13
target cable, header design
C-2 to C-3
enabling, parity
5-18
enhanced instructions
A-5
external memory interface module
2-7
external memory interface timings
4-18
F
features, emulation
2-10
flow charts, TMS320 ROM code procedural
B-2
G
global data memory
3-2, 3-9
configuration
3-9
global memory allocation register (GREG)
3-9
global memory allocation register (GREG)
3-7, 3-9
GREG
3-7, 3-9
H
header
14-pin
C-2
dimensions, 14-pin
C-2
I
I/O space, instructions
transfer data from data memory to I/O space
(OUT)
7-131
transfer data from I/O space to data memory
(IN)
7-68
I/O space memory
3-11
IDLE instruction
7-67
IEEE 1149.1 specification, bus slave device
rules
C-4
IFR
3-7, 5-17 to 5-20
immediate addressing
6-2
IMR
3-7, 5-19 to 5-20
IN instruction
7-68
indirect addressing
description
6-9
effects on auxiliary register pointer (ARP)
6-13
to 6-15



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