OR4 datasheet(106/152 Pages) LATTICE

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106

Lattice Semiconductor

Data Sheet

May, 2006

ORCA Series 4 FPGAs

Pin Information (continued)

Table 66. ORCA Series 4 I/Os Summary

Note: Each VREF pin required reduces the available user I/Os.

As shown in the Pair column, differential pairs and physical locations are numbered within each bank (e.g.,

L19C_A0 is the nineteenth pair in an associated bank). The C indicates complementary differential whereas a T

indicates true differential. The _A0 indicates the physical location of adjacent balls in either the horizontal or vertical

direction. Other physical indicators are as follows:

■

_A1 indicates one ball between pairs.

■

_A2 indicates two balls between pairs.

■

_D0 indicates balls are diagonally adjacent.

■

_D1 indicates diagonally adjacent separated by one physical ball.

VREF pins, shown in the Additional Function column, are associated to the bank and group (e.g., VREF_TL_01 is

the VREF for group one of the top left (TL) bank).

Device

352 PBGA

416 PBGAM

680 PBGAM

OR4E02/OR4E04/OR4E06

User I/O Single Ended

262

290

466 (4E4, 4E6)

405 (4E2)

User I/O Differential Pairs (LVDS,

LVPECL)

128

139

197 (4E4, 4E6)

195 (4E2)

Conﬁguration

Dedicated Function

VDD15

VDD33

VDDIO

VSS

Single-ended/Differential I/O per Bank

Bank 0

39/19

46/22

68/32

Bank 1

26/13

28/14

47/20

Bank 2

32/16

35/17

54/24 (23 for 4E2)

Bank 3

33/16

37/18

63/22 (21 for 4E2)

Bank 4

34/16

38/17

52/22

Bank 5

24/12

44/18

Bank 6

40/19

45/21

76/32

Bank 7

34/17

37/18

62/27

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