SH7727 datasheet(145/1109 Pages) RENESAS

145 / 1109 page

Section 2 CPU

Rev. 5.00 Dec 12, 2005 page 73 of 1034

REJ09B0254-0500

Notes: 1. The normal minimum number of execution cycles is two, but five cycles are required

when the operation result is read from the MAC register immediately after the

instruction.

2. The normal minimum number of execution cycles is one, but three cycles are required

when the operation result is read from the MAC register immediately after the MUL

instruction.

Logic Operation Instructions

Table 2.22 Logic Operation Instructions

Instruction

Operation

Code

Privileged

Mode

Cycles T Bit

AND

Rm,Rn

Rn & Rm

→ Rn

0010nnnnmmmm1001

—1

—

AND

#imm,R0

R0 & imm

→ R0

11001001iiiiiiii

—1

—

AND.B #imm,@(R0,GBR)

(R0 + GBR) & imm

→

(R0 + GBR)

11001101iiiiiiii

—3

—

NOT

Rm,Rn

~Rm

→ Rn

0110nnnnmmmm0111

—1

—

Rm,Rn

Rn | Rm

→ Rn

0010nnnnmmmm1011

—1

—

#imm,R0

R0 | imm

→ R0

11001011iiiiiiii

—1

—

OR.B

#imm,@(R0,GBR)

(R0 + GBR) | imm

→

(R0 + GBR)

11001111iiiiiiii

—3

—

TAS.B @Rn

If (Rn) is 0, 1

→ T;

→ MSB of (Rn)

0100nnnn00011011

—4

Test

result

TST

Rm,Rn

Rn & Rm; if the result

is 0, 1

→ T

0010nnnnmmmm1000

—1

Test

result

TST

#imm,R0

R0 & imm; if the result

is 0, 1

→ T

11001000iiiiiiii

—1

Test

result

TST.B #imm,@(R0,GBR)

(R0 + GBR) & imm;

if the result is 0, 1

→ T

11001100iiiiiiii

—3

Test

result

XOR

Rm,Rn

Rn ^ Rm

→ Rn

0010nnnnmmmm1010

—1

—

XOR

#imm,R0

R0 ^ imm

→ R0

11001010iiiiiiii

—1

—

XOR.B #imm,@(R0,GBR)

(R0 + GBR) ^ imm

→

(R0 + GBR)

11001110iiiiiiii

—3

—

Note:

* An on-chip DMAC bus cycle is not inserted between a TAS instruction operand read

cycle and write cycle. Also, bus release is not performed by

BREQ.

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