HD6433713 datasheet(118/324 Pages) RENESAS

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7.1.1 Port Types and Mask Options

The choice of I/O pin options and the resulting states are shown in table 7-2.

Upon reset, the PDR, PCR, and PMR registers are initialized, cancelling the choices of peripheral

functions. When the chip goes to a low-power mode, the on-chip peripheral function input gates

are always on, so unless input levels are fixed there will be an increase in dissipated current.

Table 7-2 Choice of I/O Port Options

For Standard I/O Pins

Class

Pins

With MOS Pull-Up (type B)

No MOS Pull-Up (type C)

I/O pins

P15, P14,

With MOS pull-up

No MOS pull-up

P11, P10,

P97 to P90

Input-only pins

P16

With MOS pull-up

No MOS pull-up

On-chip peripheral

SCK2, SCK1

With MOS pull-up

No MOS pull-up

function I/O pins

(output mode)*

On-chip peripheral

SO2, SO1,

With MOS pull-up

No MOS pull-up

function output pins

PWM, TMOE

On-chip peripheral

SCK2, SCK1

With MOS pull-up

No MOS pull-up

function input pins

(input mode)*

SI2, SI1,

IRQ5, IRQ4,

IRQ1, IRQ0

UD,

EVENT

Note: If external clock input mode is selected when the serial communication interface is used,

pins SCK2 and SCK1 will be input-only pins.

For High-Voltage Pins

Class

Pins

No MOS Pull-Down (type D)

With MOS Pull-Down (type E)

I/O pins

P47 to P40,

No MOS pull-down

With MOS pull-down.

P57 to P50,

Source of pull-down transistor

P67 to P60,

connected to Vdisp power

P77 to P70

supply.

Input-only pins

P17

No MOS pull-down

Connected to Vdisp power

supply.

On-chip peripheral

FS23 to FS0, No MOS pull-down

With MOS pull-down.

function output pins FD15 to FD0

Source of pull-down transistor

connected to Vdisp power

supply.

107

HD6433713 Datasheet(PDF) 118 Page - Renesas Technology Corp

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