HD6433713 datasheet(219/324 Pages) RENESAS

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12.2.2 VFD Segment Control Register (VFSR)

VFSR is an 8-bit read/write register for control of segment output.

Upon reset, VFSR is initialized to H'20.

Bit 7: VFD/port switching flag (VFLAG)

Bit 7 designates whether pins Pnn/FDnn and Pnn/FSnn are used as VFD pins (FDnn, FSnn) or as

general-purpose ports (Pnn).

Bit 7

VFLAG

Description

All of pins Pnn/FDnn and all of pins Pnn/FSnn function as

(initial value)

general-purpose ports.

Pnn/FDnn and Pnn/FSnn function as VFD pins according to the designations in bits

DR3 to DR0 in the VFD digit control register (VFDR), bits SR4 to SR0 in VFSR, and

bits DBR3 to DBR0 in the digit beginning register (DBR).

Note:

Even when this flag is set to 1, during a key scan interval the segment pins function as

general-purpose ports; for this reason, when this flag is read during a key scan interval it

Bit 6: Key scan enable (KSE)

Bit 6 enables or disables the addition of a key scan interval (Tdigit) to the VFD operation frame

specified by the combination of bits DR3 to DR0 in the VFD digit control register, bits SR4 to

SR0 in the VFD segment control register, and bits DBR3 to DBR0 in the digit beginning register.

Bit 6

KSE

Description

No key scan interval.

(initial value)

A key scan interval can be added. See also under bit 7 (VFLAG) above.

Bit 5: Reserved bit

Bit 5 is reserved; it always reads 1, and cannot be modified.

Bit

Initial value

Read/Write

VFLAG

R/W

KSE

R/W

—

SR4

R/W

SR3

R/W

SR0

R/W

SR2

R/W

SR1

R/W

208

HD6433713 Datasheet(PDF) 219 Page - Renesas Technology Corp

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