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HD6433713 Datasheet(PDF) 223 Page - Renesas Technology Corp |
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HD6433713 Datasheet(HTML) 223 Page - Renesas Technology Corp |
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223 / 324 page  12.3 Operation 12.3.1 Overview The VFD controller/driver may use up to 24 segment pins (FS) and up to 16 digit pins (FD). Of these, 8 pins may be used as either segment or digit pins; their function is switched in the digit beginning register (DBR). The 32 pins assigned to the VFD controller are high-voltage, high- current pins capable of directly driving a VFD. 12.3.2 Control Section The control section consists of the VFD digit control register (VFDR), VFD segment control register (VFSR), digit beginning register (DBR), display timing generator circuit, and VFD display RAM (see figure 12-1). Display timing is determined by the number of digits per frame. When the key scan feature is activated, the frame is extended by one digit; during that interval only, segment pins and digit pins may be used as general purpose ports by the CPU. These pins are in the non-illuminating state (pulled down) during the key scan interval. 12.3.3 RAM Bit Correspondence to Digits/Segments VFD display data is set in the VFD display RAM at addresses H'FEC0 through H'FEFF. Table 12-3 shows the correspondence between digit/segment pins and the VFD display RAM bits. 212 |
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