HD6433713 datasheet(227/324 Pages) RENESAS

227 / 324 page

13.1.2 Block Diagram

Figure 13-1 shows a block diagram of the A/D converter.

Figure 13-1 Block Diagram of A/D Converter

P00/AN0

Port

MPX

PMR0 (8b)

AMR (4b)

P01/AN1

P02/AN2

P03/AN3

P04/AN4

P05/AN5

P06/AN6

P07/AN7

Reference voltage

AVCC

AVSS

VREF

R255

R254

R253

R252

R251

–

ADSR

Control logic

Chopper-type comparator

Successive approximation finds the input

voltage by changing a reference voltage

REF

RESET

LPM (low-power mode)

Interrupt

Control circuitry

(successive

approximation,

interrupt request, etc.)

One of 256 switches is selected by binary search.

The reference voltage value resulting from eight

comparisons is set in ADDR.

(The eighth value is equal to the analog input

voltage.)

The internal ladder resistance is 35 k

to 40 k

typ (approximately).

Upon reset and in low-power operation modes (sleep, watch, subactive,

or standby modes), the ladder resistance is disconnected from AV

ΩΩ

by a switching transistor. The AV

current at this time is a leakage current

Alcc of 1 A or less (approximate value).

Notation:

PMR0:

AMR:

ADSR:

ADRR:

IRRAD:

RESET:

LPM:

Port mode register 0

A/D mode register

A/D start register

A/D result register

A/D conversion end interrupt request flag (interrupt request register 3)

Signal set to 1 upon reset

Signal set to 1 in low-power modes

ADRR

216

HD6433713 Datasheet(PDF) 227 Page - Renesas Technology Corp

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