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HD6433713 Datasheet(PDF) 230 Page - Renesas Technology Corp |
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HD6433713 Datasheet(HTML) 230 Page - Renesas Technology Corp |
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230 / 324 page  Bit 7: Clock select (AMR7) Bit 7 sets the A/D conversion speed.*1 Bit 7 AMR7 Conversion Period*2 φ = 2 MHz φ = 4 MHz 0 62/ φ 31 µs 14.8 µs (initial value) 1 31/ φ 15.5 µs —*1 Notes: 1. Operation is not guaranteed if the conversion time is less than 14.8 µs. Set bit 7 for a value of at least 14.8 µs. 2. A/D conversion starts after a value of 1 is written to ADSF. The conversion period starts when the start flag is set and ends when it is reset upon completion of conversion. The actual time during which sample and hold are repeated is called the conversion interval (see figure 13-2). Figure 13-2 Internal Operation of A/D Converter State Conversion interval Conversion period (31 or 62 states) Interrupt request flag IRQ sampling (CPU) When conversion is complete, the start flag is reset and the interrupt request flag is set. An interrupt is recognized by the CPU in the last instruction execution state, and interrupt exception handling is executed after that instruction is completed. Note: IRQ sampling: MOV B. Instruction execution WRITE Start flag 219 |
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