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HD6433713 Datasheet(PDF) 229 Page - Renesas Technology Corp |
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HD6433713 Datasheet(HTML) 229 Page - Renesas Technology Corp |
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229 / 324 page  13.2 Register Descriptions 13.2.1 A/D Result Register (ADRR) Note: * Not fixed The A/D result register (ADRR) is an 8-bit read-only register for holding the result of analog-to- digital conversion. ADRR can be read by the CPU at any time, but the ADRR value during A/D conversion is not fixed. After A/D conversion is complete, the conversion result is stored in ADRR as 8-bit data; this data is held in ADRR until the next conversion operation starts. ADRR is not cleared on reset. 13.2.2 A/D Mode Register (AMR) AMR is an 8-bit read/write register for selecting the A/D conversion speed and analog input pin. Writing to AMR should be done with the A/D start flag (ADSF) cleared to 0 in the A/D start register (ADSR). Upon reset, AMR is initialized to H'78. Bit Initial value Read/Write 7 ADR7 R 6 ADR6 R 5 ADR5 R 4 ADR4 R 3 ADR3 R 0 ADR0 R 2 ADR2 R 1 ADR1 R ** * * * * * * Bit Initial value Read/Write 7 AMR7 0 R/W 6 — 1 — 5 — 1 — 4 — 1 — 3 — 1 — 0 AMR0 0 R/W 2 AMR2 0 R/W 1 AMR1 0 R/W 218 |
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