| Electronic Components Datasheet Search |
|
HD6433713 Datasheet(PDF) 225 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
HD6433713 Datasheet(HTML) 225 Page - Renesas Technology Corp |
|
225 / 324 page ![]() 12.3.4 Procedure for Starting Operation The procedure for starting operation of the VFD controller/driver is given below for a case in which digit pins FD3 to FD15 and segment pins FS5 to FS23 are used. It is assumed that data has already been written to the VFD display RAM area. • Select the digit/key-scan time and dimmer resolution with bit FLMO of the VFD digit control register (VFDR), and select the digit waveform with bits DM2 to DM0. Clear bits DR3 to DR0 to 0000, making pins FD0 to FD15 operational. • Set the VFLAG bit of the VFD segment control register (VFSR) to 1, making the selected pins valid as VFD pins. Set bit KSE to enable or disable the key scan interval. Set bits SR4 to SR0 to 11011, making pins FS0 to FS23 operational. • Set bits DBR3 to DBR0 in the digit beginning register (DBR) to 0011, designating pin FD3 as the first digit pin and pin FS5 as the first segment pin. Set bit DISP to 1, turning the display on, and set bit VFDE to 1, starting VFD controller/driver operation. 12.4 Interrupts When the key scan interval starts, bit IRRKS in interrupt request register 3 (IRR3) is set to 1. These VFD interrupt requests can be enabled or disabled by means of bit IENKS of interrupt enable register 3 (IENR3). For further details, see 3.2.2, Interrupts. 12.5 Occurrence of Flicker when VFD Registers are Rewritten The VFD controller/driver is initialized whenever one of its registers (VFDR, VFSR, DBR) is rewritten. If this initialization takes place while a digit is being displayed, the contents displayed just prior to initialization will in some cases remain as an after-image in other digits. (This depends in part on the performance of the vacuum fluorescent display, but a momentary glow may be visible.) Frequent rewriting of the registers can make these after-images bright enough to appear as a false display. This problem can be avoided by employing the following programming sequence when VFD controller/driver registers are rewritten. Step Description 1. DISP = 0 2. VFLAG = 0 3. Rewrite register (FLMO, DM0 to DM3, etc.) 4. Wait for at least Tdigit (display time of one digit). (Execute other routines.) If the wait time is too long, the entire display may flicker. If the key scan feature is activated, this wait time does not have to be specially programmed. 5. VFLAG = 1 6. DISP = 1 214 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |