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HD6433713 Datasheet(PDF) 215 Page - Renesas Technology Corp |
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HD6433713 Datasheet(HTML) 215 Page - Renesas Technology Corp |
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215 / 324 page  12.1.3 Pin Configuration Table 12-1 shows the VFD controller/driver pin configuration. Table 12-1 Pin Configuration Name Abbrev. I/O Function Digit/segment pins FD0/FS7 to FD7/FS0 Output Digit or segment pins for vacuum fluorescent display (function selected in DBR for each bit) Digit pins FD8 to FD15 Output Digit pins for vacuum fluorescent display Segment pins FS8 to FS23 Output Segment pins for vacuum fluorescent display 12.1.4 Register Configuration Table 12-2 shows the VFD controller/driver register configuration. Table 12-2 Register Configuration Name Abbrev. R/W Initial Value Address VFD display RAM — R/W Not fixed H'FEC0 to H'FEFF VFD segment control register VFSR R/W H'20 H'FFB9 VFD digit control register VFDR R/W H'00 H'FFBA Digit beginning register DBR R/W H'20 H'FFBB 204 |
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