HD6433713 datasheet(213/324 Pages) RENESAS

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When an external clock source is used, after bit STF is set, data is received in synchronization

with the clock input at pin SCK2. After receiving is completed, no further receive operations take

place until bit STF is again set, even if the serial clock continues to be input.

An attempt to read or write the data buffer during receiving will cause bit IRRS2 in IRR3 and bit

WT in STSR to be set to 1. Bit OVR in STSR is set to 1 if an overrun error occurs.

When SCI2 operates on an internal clock and is in transmit mode, a gap may be inserted at data

divisions (every 8 bits or 16 bits). During this gap, serial clock stays at the high level for a

designated number of clock cycles (see figures 11-4 through 11-6).

Gap insertion and the length of the gap are designated in bits GAP2 and GAP1 of SCR2. Bit GIT

of STSR designates whether gaps occur at 8-bit or 16-bit intervals.

11.4 Interrupts

SCI2 can generate interrupts when a transfer is completed and when the data buffer is read or

written during a transfer. These interrupts are assigned to the same vector address.

When the above conditions occur, bit IRRS2 in interrupt request register 3 (IRR3) is set to 1.

SCI2 interrupt requests can be enabled or disabled in bit IENS2 of interrupt enable register 3

(IENR3). For further details, see 3.2.2, Interrupts.

When an overrun error occurs, or when a read or write of the data buffer is attempted during a

transfer, the OVR or WT bit in the status register (STSR) is set to 1. These bits can be used to

determine the cause of the error.

11.5 Application Notes

Do not write to any register during a transfer (while bit STF of STSR is set to 1), since this

can cause misoperation.

When receiving, set bit SI2 in port mode register 2 (PMR2) to 1 and clear bit CS in port mode

the

CS pin function, incorrect data will be received.

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HD6433713 Datasheet(PDF) 213 Page - Renesas Technology Corp