HD6433713 datasheet(212/324 Pages) RENESAS

212 / 324 page

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After data transmission is complete, bit IRRS2 in interrupt request register 3 (IRR3) is set to

1, and bit STF in STSR is cleared to 0.

If an internal clock source is used, a serial clock is output from pin SCK2 in synchronization with

the transmit data. After data transmission is completed, the serial clock is not output until bit STF

is again set. During this time, pin SO2 continues to output the value of the last bit transmitted.

When an external clock source is used, data is transmitted in synchronization with the serial clock

input at pin SCK2. After data transmission is completed, further transmission does not take place

even if the serial clock continues to be input; pin SO2 continues to output the value of the last bit

transmitted.

Between transmissions, the output value of pin SO2 can be changed by rewriting bit SO2 LAST

BIT in STSR.

An attempt to read or write the data buffer during transmission will cause bit IRRS2 in IRR3 to be

set to 1. Bit WT in STSR will also be set to 1.

Receiving

A receive operation is carried out as follows.

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Set bit SI2 in port mode register 2 (PMR2) to 1, making pin P95/SI1/CS the SI2 input pin.

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Allocate an area to hold the received data in the 32-byte data buffer and set the start address in

the lower 5 bits of the start address register (STAR).

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Set the transfer end address in the lower 5 bits of the end address register (EDAR).

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In serial control register 2 (SCR2), select receive mode (bit I/O = 0) and the serial clock.

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Set bit STF of the status register (STSR) to 1, starting the receive operation.

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After receiving is completed, bit IRRS2 in interrupt request register 3 (IRR3) is set to 1, and

bit STF is cleared to 0.

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Read the received data from the data buffer.

If an internal clock source is used, setting bit STF to 1 in STSR immediately starts a data receive

operation. The serial clock is output from pin SCK2.

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HD6433713 Datasheet(PDF) 212 Page - Renesas Technology Corp