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HD6433713 Datasheet(PDF) 209 Page - Renesas Technology Corp |
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HD6433713 Datasheet(HTML) 209 Page - Renesas Technology Corp |
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209 / 324 page  Figure 11-2 Operation When Start Address Exceeds End Address 11.3.2 Clock Three internal clock sources or an external clock may be selected as the serial clock. When an internal clock is selected, pin SCK2 becomes the clock output pin. 11.3.3 Data Transfer Format Figure 11-3 shows the SCI2 data transfer format. Data is sent and received starting from the least significant bit, in LSB-first format. Transmit data is output from one falling edge of the serial clock until the next falling edge. Receive data is latched at the rising edge of the clock. When SCI2 operates on an internal clock and is in transmit mode, a gap may be inserted at data divisions (every 8 bits or 16 bits). During this gap, the serial clock stays at the high level for a designated number of clock cycles (see figures 11-4 through 11-6). The CS output remains low during the gap. Gap insertion and the length of the gap are designated in bits GAP2 and GAP1 in serial control register 2 (SCR2). Bit GIT in the status register (STSR) designates whether gaps occur at 8-bit or 16-bit intervals. H'FF80 H'FF9F H'00 H'1F End address Start address End Start 198 |
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