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HD6433713 Datasheet(PDF) 210 Page - Renesas Technology Corp |
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HD6433713 Datasheet(HTML) 210 Page - Renesas Technology Corp |
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210 / 324 page ![]() Figure 11-3 Synchronous Data Transfer Format Figure 11-4 1-Clock Gap Insertion (Bits GAP2 and GAP1 = 01) Figure 11-5 2-Clock Gap Insertion (Bits GAP2 and GAP1 = 10) SCK output SO SI input data latch timing 2 2 2 Does not go to low level Bit 14 (Bit 6) Bit 15 (Bit 7)* Bit 16 (Bit 8) Bit 17 (Bit 9) Note: * When bit GIT = 1, a gap is inserted at 8-bit intervals. SCK output SO SI input data latch timing 2 2 2 Does not go to low level Bit 14 (Bit 6) Bit 15 (Bit 7)* Bit 16 (Bit 8) Note: * When bit GIT = 1, a gap is inserted at 8-bit intervals. CS SCK2 SO2 Don’t care Held Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 199 |
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