HD6433713 datasheet(208/324 Pages) RENESAS

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11.3 Operation

11.3.1 Overview

SCI2 has a 32-byte data buffer, making possible continuous transfer of up to 32 bytes of data with

one operation. SCI2 transmits and receives data in synchronization with clock pulses.

Selection of transmit or receive mode and of the serial clock is made in serial control register 2

(SCR2).

The start address register (STAR) and end address register (EDAR) designate the area within the

32-byte data buffer for holding transfer data. The address range from H'FF80 to H'FF9F is

allocated to this data buffer. The start and end positions of the transfer data area are indicated in

the lower 5 bits of STAR and EDAR.

After parameters have been set in port mode register 2 (PMR2), port mode register 3 (PMR3),

SCR2, STAR, and EDAR, then when the STF bit of the status register (STSR) is set to 1, SCI2

begins a transfer operation. STF remains set to 1 during the transfer, and is cleared to 0 when the

transfer is complete. The STF bit can therefore be used as a busy flag. Clearing the STF bit to 0

during a transfer stops the transfer operation and initializes SCI2. The contents of the data buffer

and of other registers are unchanged in this case.

During a transfer, the CPU cannot read or write the data buffer. If a write instruction is issued it is

ignored; it has the same effect as a NOP instruction except that it takes more states. Read access

during a transfer yields H'FF.

When the transfer is complete, or if a data buffer read or write is attempted during the transfer, bit

IRRS2 in interrupt request register 3 (IRR3) is set to 1. In case of an overrun error or a data buffer

read or write during the transfer, bit OVR or WT of STSR is set to 1.

Note: If the start address is set to a value higher than the end address, the result is as shown in

figure 11-2. The data transfer wraps around from address H'FF9F to address H'FF80 and

continues to the end address.

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HD6433713 Datasheet(PDF) 208 Page - Renesas Technology Corp