HD6433713 datasheet(204/324 Pages) RENESAS

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Bits 1 and 0: Serial clock select (PS1 to PS0)

Bits 1 and 0 select one of three internal clock sources or an external clock.

Serial Clock Period

PS1

PS0

Pin SCK2

Clock Source

φ = 4 MHz φ = 2 MHz φ = 1 MHz

SCK2 output

Prescaler S

φ/2 (initial value) *

1 µs

2 µs

SCK2 output

Prescaler S

φ/4

1 µs

2 µs

4 µs

SCK2 output

Prescaler S

φ/8

2 µs

4 µs

8 µs

SCK2 input

External clock

—

Note: * Can be set, but operation is not guaranteed.

11.2.4 Status Register (STSR)

Notes: 1. Not fixed

2. Cleared to 0 by write operation to STSR.

STSR is an 8-bit register indicating the SCI2 operation state, error status, etc. Writing to this

Upon reset, STSR is initialized to H'E0 or H'E8.

Bits 7 to 5: Reserved bits

Bits 7 to 5 are reserved; they always read 1, and cannot be modified.

Bit 4: Extended data bit (SO2 LAST BIT)

Bit 4 holds the last bit of transmitted data after transmission ends.

Output from pin SO2 can be altered by software by modifying this bit either before or after

transmission.

Writing to this bit during data transmission may cause misoperation.

Bit 1 Bit 2

Prescaler

PS1

PS0

Divider Ratio

Bit

Initial value

Read/Write

—

R/W

OVR

R/W*2

STF

R/W

R/W*2

GIT

R/W

SO2 LAST

BIT

193

HD6433713 Datasheet(PDF) 204 Page - Renesas Technology Corp

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