HD6433713 datasheet(203/324 Pages) RENESAS

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11.2.3 Serial Control Register 2 (SCR2)

SCR2 is an 8-bit read/write register, for selecting whether SCI2 transmits or receives, for gap

insertion during continuous transfer, and for serial clock selection.

Upon reset, SCR2 is initialized to H'E0.

Bits 7 to 5: Reserved bits

Bits 7 to 5 are reserved; they always read 1, and cannot be modified.

Bit 4: Transmit/receive select (I/O)

Bit 4 selects SCI2 transmit or receive mode.

Bit 4

I/O

Description

SCI2 is in receive mode.

(initial value)

SCI2 is in transmit mode.

Bits 3 and 2: Gap select (GAP2 to GAP1)

When data is transmitted or received continuously, gaps can be inserted at data divisions by

holding the serial clock high for a length of time designated by bits 3 and 2. Bits 3 and 2 are valid

when an internal clock source is selected as the serial clock (PS1 and 0

≠ 11).

Data divisions may be placed every 8 bits or 16 bits; this is selected in bit GIT in the status

Bit 3

Bit 2

GAP2

GAP1

Description

Serial clock keeps the same duty cycle even at data divisions.

(initial value)

Serial clock high level extended by one clock cycle at data divisions.

Serial clock high level extended by two clock cycles at data divisions.

Serial clock high level extended by eight clock cycles at data divisions.

Bit

Initial value

Read/Write

—

I/O

R/W

GAP2

R/W

PS0

R/W

GAP1

R/W

PS1

R/W

192

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