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7630 Datasheet(PDF) 186 Page - Renesas Technology Corp |
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7630 Datasheet(HTML) 186 Page - Renesas Technology Corp |
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186 / 238 page ![]() 3-15 APPENDIX 3.3 Notes on use 7630 Group User’s Manual 3.3.5 Notes on programming (1) Initialization of processor status register Flags which affect program execution must be initialized after a reset. In particular, it is essential to initialize the T and D flags because they have an important effect on calculations. Reason After a reset, the contents of the processor status register (PS) are undefined except for the I flag which is “1”. Fig. 3.3.1 Stack memory contents after instruction execution (2) How to reference the processor status register To reference the contents of the processor status register (PS), execute the PHP instruction once then read the contents of (S)+1. If necessary, execute the PLP instruction to return the PS to its original status. A NOP instruction must be executed after every PLP instruction. Reset Main program Initializing of flags NOP PLP instruction execution Stored PS (S) (S) + 1 (2) Modifying output data with bit managing When the data register (port latch) of an I/O port is modified with the bit managing instruction52, the value of the unspecified bit may be changed. Reason The bit managing instructions are read-modify-write form instructions for reading and writing data by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an I/O port, the following is executed to all bits of the data register. • As for a bit which is set for an input port: The pin state is read in the CPU, and is written to this bit after bit managing. • As for a bit which is set for an output port: The bit value is read in the CPU, and is written to this bit after bit managing. Note the following : • Even when a port which is set as an output port is changed for an input port, its data register holds the output data. • As for a bit of which is set for an input port, its value may be changed even when not specified with a bit managing instruction in case where the pin state differs from its data register contents. 52 bit managing instructions : SEB, and CLB instructions |
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