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HC210 Datasheet(PDF) 106 Page - Altera Corporation |
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HC210 Datasheet(HTML) 106 Page - Altera Corporation |
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106 / 228 page ![]() 5–14 Altera Corporation September 2008 HardCopy Series Handbook, Volume 1 1 For more information on how to switch to TimeQuest, refer to the Switching to the TimeQuest Timing Analyzer chapter of the Quartus II Handbook, volume 3, on the Altera website at www.altera.com . When you specify the TimeQuest analyzer as the timing analysis tool, the TimeQuest analyzer guides the Fitter and analyzes timing results after compilation. TimeQuest The TimeQuest Timing Analyzer is a powerful ASIC-style timing analysis tool that validates timing in your design by using an industry-standard constraint, analysis, and reporting methodology. You can use the TimeQuest Timing Analyzer’s GUI or command-line interface to constrain, analyze, and report results for all timing paths in your design. Before running the TimeQuest Timing Analyzer, you must specify initial timing constraints that describe the clock characteristics, timing exceptions, and signal transition arrival and required times. You can specify timing constraints in the Synopsys Design Constraints (SDC) file format using the GUI or command-line interface. The Quartus II Fitter optimizes the placement of logic to meet your constraints. During timing analysis, the TimeQuest Timing Analyzer analyzes the timing paths in the design, calculates the propagation delay along each path, checks for timing constraint violations, and reports timing results as slack in the Report pane and in the Console pane. If the TimeQuest Timing Analyzer reports any timing violations, you can customize the reporting to view precise timing information about specific paths, and then constrain those paths to correct the violations. When your design is free of timing violations, you can be confident that the logic will operate as intended in the target device. The TimeQuest Timing Analyzer is a complete static timing analysis tool that you can use as a sign-off tool for Altera FPGAs and structured ASICs. Setting Up the TimeQuest Timing Analyzer If you want use TimeQuest for timing analysis, from the Assignments tab in the Quartus II software, click on Timing Analysis Settings, and in the pop-up window, click the Use TimeQuest Timing Analyzer during compilation tab. |
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