HC210 datasheet(107/228 Pages) ALTERA

107 / 228 page

Altera Corporation

5–15

September 2008

HardCopy II Recommended Settings in the Quartus II Software

Use the following Tcl command to use TimeQuest as your timing analysis

engine:

set_global_assignment -name \

USE_TIMEQUEST_TIMING_ANALYZER ON

You can launch the TimeQuest analyzer in one of the following modes:

■

Directly from the Quartus II software

■

Stand-alone mode

■

Command-line mode

In order to perform a thorough Static Timing Analysis, you would need

to specify all the timing requirements. The most important timing

requirements are clocks and generated clocks, input and output delays,

false paths and multi-cycle paths, minimum and maximum delays.

In TimeQuest, clock latency, and recovery and removal analysis are

enabled by default.

For more information about TimeQuest, refer to the Quartus II TimeQuest

Timing Analyzer chapter in volume 3 of the Quartus II Handbook on the

Altera website at www.altera.com.

Constraints for Clock Effect Characteristics

The

create_clock, create_generated_clock commands create

ideal clocks and do not account for board effects. In order to account for

clock effect characteristics, you can use the following commands:

■

set_clock_latency

■

set_clock_uncertainty

For more information about how to use these commands, refer

to the Quartus II TimeQuest Timing Analyzer chapter in volume 3

of the Quartus II Handbook.

Beginning in Quartus II version 7.1, you can use the new command

erive_clock_uncertainty to automatically derive the clock

uncertainties. This command is useful when you are not sure what the

clock uncertainties might be. The calculated clock uncertainty values are

based on I/O buffer, static phase errors (SPE) and jitter in the PLL's, clock

networks, and core noises.

HC210 Datasheet(PDF) 107 Page - Altera Corporation

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