HC210 datasheet(156/228 Pages) ALTERA

156 / 228 page

6–28

Altera Corporation

September 2008

HardCopy Series Handbook, Volume 1

This command initializes the database for the HardCopy II revision and

creates a new QSF file (in this example, demo_design_hcii.qsf), ensuring

that all constraints for the Stratix II FPGA revision are ported over.

Next, the current working revision for the Quartus II project is changed

to the HardCopy II revision and the design is compiled for the

HardCopy II device target:

tcl> set_current_revision demo_design_hcii

tcl> execute_flow -compile

As with the prototype Stratix II revision, report files are generated in the

project directory for each of the tools that are executed.

Understanding

Report Files

The

execute_flow command generates a number of report files in the

project directory. These files summarize messages displayed on the

console during compilation and provide additional information about

the design. The name of each report file follows the format

<revision><tool short name>.summary and <revision><tool short name>.rpt,

where <revision> is the revision name of the current design. The

.summary

file contains a brief summary of messages and results from the

tool while the .rpt file contains more detailed messages and information.

For a HardCopy II project, two sets of report files are generated: one for

the Stratix II prototype FPGA revision and one for the HardCopy II

revision. Table 6–9 describes the different report files.

The Tcl report package provides a powerful collection of

procedures for customizing and managing report files related to

the Quartus II fitter and timing analysis engines.

For more information on customizing and managing report files, refer to

the Tcl Packages and Commands report section of the Quartus II Tcl

Reference Manual.

Table 6–9. Stratix II Compile Report File Descriptions

(Part 1 of 2)

Switch

Tool

Description

<revision>.map.rpt

Analysis & Synthesis

Synthesis settings, source files, messages, and resource usage.

<revision>.map.eqn Analysis & Synthesis

Implementation equations and device resource instantiations.

<revision>.fit.rpt

Fitter

Fitter settings, layout optimizations, resources, pin-out, and

messages.

<revision>.fit.eqn

Fitter

Implemented equations and device resource instantiations after

fitting.

<revision>.drc.rpt

Design Assistant

Design rule settings, violations, and messages.

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