HC210 datasheet(152/228 Pages) ALTERA

152 / 228 page

6–24

Altera Corporation

September 2008

HardCopy Series Handbook, Volume 1

To change these default settings, refer to the Timing Settings section in the

Quartus II Support of HardCopy Series Devices chapter in volume 1 of the

Quartus II Handbook.

In TimeQuest, the constraint set_false_path is used to describe paths that

should not be included in timing optimization or analysis. The syntax for

this constraint is:

tcl> set_false_path \

[-from <from list>] \

[-to <to list>] \

[-thru <thru list>]

In Classic Timing Analyzer, the most common command for controlling

false paths is the set_timing_cut_assignment command. The syntax for

this command is:

tcl> set_timing_cut_assignment \

[-comment <comment>] \

[-disable] \

[-from <from_pin_list>] \

[-remove] \

[-to <to_pin_list>]

All paths between nodes in the <from_pin_list> to nodes in the

<to_pin_list> are excluded from timing optimization and analysis

operations.

Example of TimeQuest SDC Constraints

# Timing Assignments

# ==================

create_clock –period 10.0ns -name ref_clk ref_clk

set_clock_latency -late 3 ref_clk

set_clock_latency -early 2 ref_clk

set_clock_uncertainty –hold –to ref_clk 0.250ns

set_clock_uncertainty –setup –to ref_clk 0.250ns

# Input delay of 6ns (max) & 2ns (min) for bus data_in[1:0]

set_input_delay –clock ref_clk –max 6 data_in

set_input_delay –clock ref_clk –min 2 data_in

# Output delay of 6ns (max) & 2ns (min) for bus data_out[1:0]

set_output_delay –clock ref_clk –max 6 data_out

set_output_delay –clock ref_clk –min 2 data_out

# Don’t care about timing on the resetn net. Set as false path

set_false_path -from resetn

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