HC210 datasheet(151/228 Pages) ALTERA

151 / 228 page

Altera Corporation

6–23

September 2008

Assigning Timing Constraints

As an example, the following Tcl script specifies input and output min

and max delays for two I/O signals. Input

data_in[0] has minimum

and maximum external delays of 3 ns and 7 ns, respectively. Output

data_out[0] has minimum and maximum external delays of 4 ns and

8 ns, respectively. The external input delays for

data_in[0] are relative

to the positive edge of clock

ref_clk and the external output delays for

data_out[0] are relative to the negative edge of clock ref_clk.

# Tcl Script Setting I/O Timing Using set_input_delay and set_output_delay

set_input_delay -clock ref_clk -max 7.0 [get_ports data_in[0]]

set_input_delay -clock ref_clk -min 3.0 [get_ports data_in[0]]

set_output_delay -clock ref_clk -max 8.0 [get_ports data_out[0]]

set_output_delay -clock ref_clk -min 4.0 [get_ports data_out[0]]

Creating Timing Exceptions

Timing exceptions are used to correct timing constraints not covered by

clock settings and I/O timing settings. The most common of these are

multicycle paths and false paths.

In TimeQuest, multicycle paths are described using the

set_multicycle_path

constraint. The syntax for this constraint is:

set_multicycle_path [-setup][-hold][-start]

In Classic Timing Analyzer, multicycle paths are described using the

set_multicycle_assignment command. The syntax for this

command is:

tcl> set_multicycle_assignment [-comment <comment>] \

[-disable] [-end] [-from <from_list>] \

[-hold] [-remove] [-setup] [-start] \

[-to <to_list>] <path_multiplier>

In either timing analyzer, multicycle assignments are made with the

-setup argument, to specify the maximum number of cycles, or with the

-hold argument, to specify the minimum number of cycles for a path.

False paths describe paths that should not be included in timing

optimization or analysis operations. In the Quartus II software, there are

a number of ways to describe false paths. By default, in Classic Timing

Analyzer, feedback from the output to input side of bidirectional I/O,

read-while-write paths through memories, and cross-clock domain paths

are not timed during optimization or timing analysis. By default, in Time

Quest, cross-clock domain paths are timed.

HC210 Datasheet(PDF) 151 Page - Altera Corporation

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