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HC210 Datasheet(PDF) 149 Page - Altera Corporation

Part # HC210
Description  HardCopy II Device Family
PDF  228 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

HC210 Datasheet(HTML) 149 Page - Altera Corporation

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Altera Corporation
6–21
September 2008
Assigning Timing Constraints
The minimum set of timing constraints for a HardCopy II design are:
■
Clock settings (FMAX) for each and every clock domain
■
Minimum and maximum delays for all I/O paths, including
asynchronous reset and control I/O signals
In addition, it is good design practice to develop timing constraints to
cover:
■
Specific cross-clock domain timing requirements
■
False paths
■
Multicycle paths
In TimeQuest, timing constraints are written in TimeQuest SDC format
and are read from an SDC file. An example file is demo_design.sdc. See
“Using TimeQuest” on page 6–30.
In the Classic Timing Analyzer, timing constraints are applied using
dedicated Tcl commands and by assigning timing-specific attributes
using the
set_instance_assignment command.
This section provides an overview of timing constraint development
using Tcl commands.
f
For more information on timing constraints, refer to the Timing Analysis
section in volume 3 of the Quartus II Handbook.
Specifying System Clocks
The most basic constraints that should be applied describe the clock for
each clock domain. Parameters usually specified for each clock are:
■
Clock period
■
Latency (
LATE_CLOCK_LATENCY/EARLY_CLOCK_LATENCY
assignments)
■
Uncertainty (
set_clock_uncertainty command)
Clock uncertainty specified with the
set_clock_uncertainty
command models any uncertainty in the clock period, including jitter,
and is often used to introduce some margin into the target clock
frequency. The following example constraints illustrate clock definition
for a design with two clock domains,
clk_a and clk_b. In this case, both
clocks run at 100 MHz, but with different clock latency and skew.
## Example TimeQuest SDC Constraints Defining Clocks clk_a and clk_b
create_clock -period 10.0 -name clk_a [get_ports clk_a]
set_clock_latency -source -late 3.0 clk_a
set_clock_latency -source -early 2.0 clk_a



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