HC210 datasheet(153/228 Pages) ALTERA

153 / 228 page

Altera Corporation

6–25

September 2008

Compiling the Stratix II Prototype Design

Example of Classic Timing Analyzer Tcl Script

# Timing Assignments

# ==================

create_base_clock –fmax 100 MHz –target ref_clk ref_clk

set_instance_assignment -name LATE_CLOCK_LATENCY 3ns -to ref_clk

set_instance_assignment -name EARLY_CLOCK_LATENCY 2ns -to ref_clk

set_clock_uncertainty –hold –to ref_clk 0.250ns

set_clock_uncertainty –setup –to ref_clk 0.250ns

# Input delay of 6ns (max) & 2ns (min) for bus data_in[1:0]

set_input_delay –clk_ref ref_clk –max –to data_in 6.0ns

set_input_delay –clk_ref ref_clk –min –to data_in 2.0ns

# Output delay of 6ns (max) & 2ns (min) for bus data_out[1:0]

set_output_delay –clk_ref ref_clk –max –to data_out 6.0ns

set_output_delay –clk_ref ref_clk –min –to data_out 2.0ns

# Don’t care about timing on the resetn net. Set as false path

set_timing_cut_assignment -from resetn

This section has provided an overview of Tcl commands for applying

timing constraints.

For more information on the application of timing constraints using Tcl

commands, refer to the Tcl Packages and Commands chapter in the

Quartus II Scripting Reference Manual.

Compiling the

Stratix II

Prototype

Design

Once all global assignments, resource assignments, and timing

assignments have been specified, the next step in the design process is to

compile the Stratix II FPGA prototype design. The

execute_flow

command is provided for this purpose and supports various arguments

affecting the compilation process. The syntax for this command is:

tcl> execute_flow \

[-analysis_and_elaboration] \

[-attempt_similar_placement] \

[-check_ios] \

[-check_netlist] \

[-compile] \

[-compile_and_simulate] \

[-early_timing_estimate] \

[-eco] [-export_database] \

[-fast_model] \

[-generate_functional_sim_netlist] \

[-import_database]

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