HC210 datasheet(150/228 Pages) ALTERA

150 / 228 page

6–22

Altera Corporation

September 2008

HardCopy Series Handbook, Volume 1

set_clock_uncertainty -to clk_a 0.25

create_clock -period 10.0 -name clk_b [get_ports clk_b]

set_clock_latency -source -late 4.0 clk_b

set_clock_latency -source -early 3.0 clk_b

set_clock_uncertainty -to clk_b 0.25

Input/Output Timing

System clock parameters define the setup and hold timing for register to

to describe I/O to register, and register to I/O timing.

The set_input_delay constraint is used to specify the delay from a source

external to the chip to an input pin, relative to a defined clock. The syntax

for this command is given below.

set_input_delay \

-clock <clock name> \

[-clock_fall] \

[-rise | -fall] \

[-max | -min] \

[-add_delay] \

[-reference_pin <pin or port>] \

<delay value> \

The <clock name> argument specifies the reference clock for the delay. The

<port pin list> argument is the top-level input signal for the design, and

<delay value> is the external delay. The external delay is measured from

the positive (rising) edge of <clock> unless the -

clock_fall argument is

specified. The

-min and -max arguments are used to specify whether

delay value> is the minimum or maximum external delay,

respectively.

The set_output_delay constraint is similar to the set_input_delay

constraint except that it specifies the delay from an output pin to its

external destination relative to a clock.

set_output_delay \

-clock <clock name> \

[-clock_fall] \

[-rise | -fall] \

[-max | -min] \

[-add_delay] \

[-reference_pin <pin or port>] \

<delay value> \

HC210 Datasheet(PDF) 150 Page - Altera Corporation

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