HC210 datasheet(165/228 Pages) ALTERA

165 / 228 page

Altera Corporation

7–1

September 2008

7. Timing Constraints for

HardCopy II Devices

Introduction

In a Stratix® II FPGA design, a complete and accurate set of timing

constraints is often not critical to achieving a fully functioning product.

The reconfigurability of the FPGA means that if a timing-related problem

occurs during hardware test and verification, the device can be

reprogrammed to correct it. No ASIC re-spin or board-level work-around

is necessary and the fix can be implemented in a timely and cost-effective

way.

In contrast, a HardCopy® II design results in a mask-programmed,

structured ASIC device. Timing problems may result in long

design-change turn-around times and high NRE costs. To ensure a

smooth transition through the Quartus® II software and back-end design

in the Altera® HardCopy Design Center (HCDC), Altera strongly

recommends that you use the TimeQuest timing analyzer provided with

the Quartus II software and that you follow the timing considerations

and timing constraint recommendations given in this chapter. Use of the

TimeQuest timing analyzer for Design Review 2 (DR2) in the

HardCopy II design flow will soon be mandatory.

The TimeQuest timing analyzer is a complete static timing analysis tool

that you can use as a sign-off tool for Altera FPGAs and structured ASICs.

As FPGA devices become denser and faster, they are the targets of

complex designs and applications that previously were implemented in

ASICs. These complex designs push the limits of the traditional Classic

Timing Analyzer, affecting designer productivity. The Quartus II

TimeQuest timing analyzer, in contrast, works well on complex designs.

Its intuitive user interface, support of industry-standard Synopsys

Design Constraints (SDC) format, and scripting capabilities all result in

increased productivity and efficiency.

For more information on the features and capabilities of the TimeQuest

timing analyzer, refer to the TimeQuest Timing Analyzer chapter in

volume 3 of the Quartus II Handbook.

This chapter includes the following information:

■

A description of timing-related differences between HardCopy II

structured ASICs and Stratix II FPGAs

■

Descriptions and a comparison of the TimeQuest timing analyzer

and the Classic Timing Analyzer

H51028-2.2

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