HC210 datasheet(208/228 Pages) ALTERA

208 / 228 page

8–20

Altera Corporation

September 2008

HardCopy Series Handbook, Volume 1

Differential I/O Termination

Similar to the FPGA, HardCopy II devices provide an on-chip 100-

differential termination option on each differential receiver channel for

LVDS and HyperTransport technology standards. When using an HC240

device as a companion device, differential termination is supported on all

row I/O pins that support LVDS and HyperTransport technology

standards.

When using HC230, HC220, and HC210 devices, only the left row I/O

pins support differential termination. The right row I/O pins do not

support LVDS and HyperTransport technology standards.

Table 8–14. HardCopy II Selectable I/O Drivers with On-Chip Series

Termination with Calibration

Note (1)

I/O Standard

HC230, HC240 Column

I/O Pins

HC210, HC220 Top

Column I/O Pins (2)

3.3-V LVTTL

25 or 50

3.3-V LVCMOS

25 or 50

2.5-V LVTTL

25 or 50

2.5-V LVCMOS

25 or 50

1.8-V LVTTL

25 or 50

1.8-V LVCMOS

25 or 50

1.5-V LVTTL

(3)

1.5-V LVCMOS

(3)

2.5-V SSTL class I

2.5-V SSTL class II

1.8-V SSTL class I

1.8-V SSTL class II

1.8-V HSTL class I

1.8-V HSTL class II

1.5-V HSTL class I

(3)

Notes to Table 8–14:

(1)

These numbers are preliminary and pending silicon characterization.

(2)

HardCopy II HC210 and HC220 devices do not support on-chip series

termination with calibration on bottom I/O pins.

(3)

Support pending HardCopy II characterization.

HC210 Datasheet(PDF) 208 Page - Altera Corporation

HC210 Datasheet(HTML) 208 Page - Altera Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL