USB3503 datasheet(22/82 Pages) SMSC

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USB 2.0 HSIC High-Speed Hub Controller Optimized for Portable Applications

Datasheet

SMSC USB3503A

Revision 1.1 (02-07-13)

DATASHEET

4.2

Standby Mode

Standby Mode provides a very low power state for maximum power efficiency when no signaling is

required. This is the lowest power state. In Standby Mode all internal regulators are powered off, the

PLL is not running, and core logic is powered down in order to reduce power. Because core logic is

powered off, no configuration settings are retained in this mode and must be re-initialized after

RESET_N is negated high.

4.2.1

External Hardware RESET_N

A valid hardware reset is defined as an assertion of RESET_N low for a minimum of 100us after all

power supplies are within operating range. While reset is asserted, the Hub (and its associated

external circuitry) enters STANDBY MODE and consumes extremely low current as defined in

Table 10.3 and Table 10.4.

Assertion of RESET_N (external pin) causes the following:

— All downstream ports are disabled.

— All transactions immediately terminate; no states are saved.

— All internal registers return to the default state.

— The PLL is halted.

After RESET_N is negated high in the Hub.Init stage, the Hub reads customer-specific data from the

ROM.

4.3

Hub Mode

Hub Mode provides functions of configuration and high speed USB hub operation including connection

and communication. Upon entering Hub Mode and initializing internal logic, the device passes through

several sequential stages based on a fixed time interval.

4.3.1

Hub Initialization Stage (Hub.Init)

The first stage is the initialization stage and occurs when Hub mode is entered based on the conditions

in Table 4.1. In this stage the 1.2V regulator is enabled and stabilizes, internal logic is reset, and the

PLL locks if a valid REFCLK is supplied. Configuration registers are initialized to their default state and

REF_SEL[1:0] input values are latched. The USB3503 will complete initialization and automatically

enter the next stage after Thubinit. Because the digital logic within the device is not yet stable, no

communication with the device using the serial port is possible. Configuration registers are initialized

to their default state.

4.3.2

Hub Wait RefClk Stage (Hub.WaitRef)

During this stage the serial port is not functional.

If the reference clock is provided before entering hub mode, the USB3503 will transition to the Hub

Configuration stage without pausing in the Hub Wait RefClk stage. Otherwise, the USB3503 will

transition to the Hub configuration stage once a valid reference clock is supplied and the PLL has

locked.

4.3.3

Hub Configuration Stage (Hub.Config)

In this stage, the SOC has an opportunity to control the configuration of the USB3503 and modify any

of the default configuration settings specified in the integrated ROM. These settings include USB

USB3503 Datasheet(PDF) 22 Page - SMSC Corporation

USB3503 Datasheet(HTML) 22 Page - SMSC Corporation

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