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W97AH6KB Datasheet(PDF) 108 Page - Winbond

Part # W97AH6KB
Description  Four-bit prefetch DDR architecture
PDF  127 Pages
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Manufacturer  WINBOND [Winbond]
Direct Link  http://www.winbond.com
Logo WINBOND - Winbond

W97AH6KB Datasheet(HTML) 108 Page - Winbond

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W97AH6KB / W97AH2KB
Publication Release Date: May 15, 2014
Revision: A01-001
- 108 -
8.7
AC Timings
8.7.1
LPDDR2 AC Timing
(Note 6 apply to the entire table)
Parameter
Symbol
min /
max
min
tCK
Data Rate
Unit
1066
933
800
667
533
400
333
Max. Frequency
*4
~
533
466
400
333
266
200
166
MHz
Clock Timing
Average Clock Period
tCK(avg)
MIN
1.875
2.15
2.5
3
3.75
5
6
nS
MAX
100
Average high pulse width
tCH(avg)
MIN
0.45
tCK(avg)
MAX
0.55
Average low pulse width
tCL(avg)
MIN
0.45
tCK(avg)
MAX
0.55
Absolute Clock Period
tCK(abs)
MIN
tCK(avg)min + tJIT(per)min
pS
Absolute clock HIGH pulse width
(with allowed jitter)
tCH(abs),
allowed
MIN
0.43
tCK(avg)
MAX
0.57
Absolute clock LOW pulse width
(with allowed jitter)
tCL(abs),
(allowed)
MIN
0.43
tCK(avg)
MAX
0.57
Clock Period Jitter
(with allowed jitter)
tJIT(per),
(allowed)
MIN
-90
-95
-100
-110
-120
-140
-150
pS
MAX
90
95
100
110
120
140
150
Maximum Clock Jitter between
two consecutive clock cycles
(with allowed jitter)
tJIT(cc),
allowed
MAX
180
190
200
220
240
280
300
pS
Duty cycle Jitter
(with allowed jitter)
tJIT(duty),
allowed
MIN
MIN ((tCH(abs),min - tCH(avg),min),
(tCL(abs),min - tCL(avg),min)) * tCK(avg)
pS
MAX
MAX ((tCH(abs),max - tCH(avg),max),
(tCL(abs),max - tCL(avg),max)) * tCK(avg)
pS
Cumulative error across 2 cycles
tERR(2per),
(allowed)
MIN
-132
-140
-147
-162
-177
-206
-221
pS
MAX
132
140
147
162
177
206
221
Cumulative error across 3 cycles
tERR(3per),
(allowed)
MIN
-157
-166
-175
-192
-210
-245
-262
pS
MAX
157
166
175
192
210
245
262
Cumulative error across 4 cycles
tERR(4per),
(allowed)
MIN
-175
-185
-194
-214
-233
-272
-291
pS
MAX
175
185
194
214
233
272
291
Cumulative error across 5 cycles
tERR(5per),
(allowed)
MIN
-188
-199
-209
-230
-251
-293
-314
pS
MAX
188
199
209
230
251
293
314
Cumulative error across 6 cycles
tERR(6per),
(allowed)
MIN
-200
-211
-222
-244
-266
-311
-333
pS
MAX
200
211
222
244
266
311
333
Cumulative error across 7 cycles
tERR(7per),
(allowed)
MIN
-209
-221
-232
-256
-279
-325
-348
pS
MAX
209
221
232
256
279
325
348
Cumulative error across 8 cycles
tERR(8per),
(allowed)
MIN
-217
-229
-241
-266
-290
-338
-362
pS
MAX
217
229
241
266
290
338
362
Cumulative error across 9 cycles
tERR(9per),
(allowed)
MIN
-224
-237
-249
-274
-299
-349
-374
pS
MAX
224
237
249
274
299
349
374
Cumulative error across 10
cycles
tERR(10per),
(allowed)
MIN
-231
-244
-257
-282
-308
-359
-385
pS
MAX
231
244
257
282
308
359
385
Cumulative error across 11
cycles
tERR(11per),
(allowed)
MIN
-237
-250
-263
-289
-316
-368
-395
pS
MAX
237
250
263
289
316
368
395
Cumulative error across 12
cycles
tERR(12per),
(allowed)
MIN
-242
-256
-269
-296
-323
-377
-403
pS
MAX
242
256
269
296
323
377
403
Cumulative error across n = 13,
14 . . . 49, 50 cycles
tERR(nper),
(allowed)
MIN
tERR(nper),allowed,min
= (1 + 0.68ln(n)) * tJIT(per),allowed,min
pS
MAX
tERR(nper),allowed,max = (1 + 0.68ln(n)) * tJIT(per),allowed,max



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