W97AH6KB datasheet(111/127 Pages) WINBOND

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W97AH6KB / W97AH2KB

Publication Release Date: May 15, 2014

Revision: A01-001

- 111 -

Parameter

Symbol

min /

max

min

tCK

Data Rate

Unit

1066

933

800

667

533

400

333

LPDDR2 Temperature De-Rating

tDQSCK De-Rating

tDQSCK

(Derated)

MAX

5620

6000

Core Timings Temperature De-Rating

tRCD

(Derated)

MIN

tRCD + 1.875

tRC

(Derated)

MIN

tRC + 1.875

tRAS

(Derated)

MIN

tRAS + 1.875

tRP

(Derated)

MIN

tRP + 1.875

tRRD

(Derated)

MIN

tRRD + 1.875

Notes:

Input set-up/hold time for signal (CA[0:n], CS_n).

CKE input setup time is measured from CKE reaching high/low voltage level to CK_t/CK_c crossing.

CKE input hold time is measured from CK_t/CK_c crossing to CKE reaching high/low voltage level.

Frequency values are for reference only. Clock cycle time (tCK) shall be used to determine device capabilities.

To guarantee device operation before the LPDDR2 device is configured a number of AC boot timing parameters are defined in this table.

Boot parameter symbols have the letter b appended, e.g. tCK during boot is tCKb.

Frequency values are for reference only. Clock cycle time (tCK or tCKb) shall be used to determine device capabilities.

The SDRAM will set some Mode register default values upon receiving a RESET (MRW)

command as specified in “Mode Register

Definition”.

The output skew parameters are measured with Ron default settings into the reference load.

The min tCK column applies only when tCK is greater than 6nS for LPDDR2-S4 devices.

10. All AC timings assume an input slew rate of 1V/nS.

11. Read, Write, and Input Setup and Hold values are referenced to Vref.

12. For low-to-high and high-to-low transitions, the timing reference will be at the point when the signal crosses VTT. tHZ and tLZ transitions

occur in the same access time (with respect to clock) as valid data transitions. These parameters are not referenced to a specific voltage

level but to the time when the device output is no longer driving (for tRPST, tHZ(DQS) and tHZ(DQ) ), or begins driving (for tRPRE, tLZ(DQS),

tLZ(DQ) ). Below

“HSUL_12 Driver Output Reference Load for Timing and Slew Rate” figure shows a method to calculate the point when

device is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS), tLZ(DQ) by measuring the signal at two different voltages. The

actual voltage measurement points are not critical as long as the calculation is consistent.

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