W97AH6KB datasheet(113/127 Pages) WINBOND

113 / 127 page

W97AH6KB / W97AH2KB

Publication Release Date: May 15, 2014

Revision: A01-001

- 113 -

8.7.2

CA and CS_n Setup, Hold and Derating

For all input signals (CA and CS_n) the total tIS (setup time) and tIH (hold time) required is calculated by adding the

data sheet tIS(base) and tIH(base) value (see 8.7.2.1

“CA and CS_n Setup and Hold Base-Values for 1V/nS” table)

to the

ΔtIS and ΔtIH derating value (see 8.7.2.2 “Derating Values LPDDR2 tIS/tIH - AC/DC Based AC220” table).

Example: tIS (total setup time) = tIS(base) +

ΔtIS.

Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and

the first crossing of VIH(ac)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the

last crossing of VREF(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew

rate line betwe

en shaded ‘VREF(dc) to ac region’, use nominal slew rate for derating value (see 8.7.2.4 “Nominal

Slew Rate and tVAC for Setup Time tIS for CA and CS_n with Respect to Clock

” figure). If the actual signal is

later than the nominal slew rate line anywhere between shaded ‘VREF(dc) to ac region’, the slew rate of a tangent line

to the actual signal from the ac level to dc level is used for derating value (see 8.7.2.6

“Tangent Line for Setup

Time tIS for CA and CS_n with Respect to Clock

” figure).

Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and

the first crossing of VREF(dc). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the

last crossing of VIH(dc)min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slew

rate line between shaded ‘dc to VREF(dc) region’, use nominal slew rate for derating value (see 8.7.2.5 “Nominal

Slew Rate for Hold Time tIH for CA and CS_n with Respect to Clock

” figure). If the actual signal is earlier than

the nominal slew rate line anywhere between shaded ‘dc to VREF(dc) region’, the slew rate of a tangent line to the

actual signal from the dc level to VREF(dc) level is used for derating value (see 8.7.2.7

“Tangent Line for Hold Time

tIH for CA and CS_n with Respect to Clock

” figure).

For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC (see 8.7.2.3

“Required

Time tVAC above VIH(ac) {below VIL(ac)} for Valid Transition

” table).

Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached

VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and

reach VIH/IL(ac).

For slew rates in between the values listed in 8.7.2.2

“Derating Values LPDDR2 tIS/tIH - AC/DC Based AC220”

table, the derating values may obtained by linear interpolation. These values are typically not subject to production

test. They are verified by design and characterization.

8.7.2.1

CA and CS_n Setup and Hold Base-Values for 1V/nS

Unit [pS]

LPDDR2-1066

LPDDR2-800

reference

tIS(base)

VIH/L(ac) = VREF(dc) ± 220mV

tIH(base)

160

VIH/L(dc) = VREF(dc) ± 130mV

Note: ac/dc referenced for 1V/nS CA and CS_n slew rate and 2V/nS differential CK_t-CK_c slew rate.

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