ADC14X250 datasheet(24/69 Pages) TI1

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ADC14X250

SLASE49 – DECEMBER 2015

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Feature Description (continued)

Figure 32. Simplified Input Differential Balance Correction Circuit

Amplitude correction is achieved by varying the single-ended termination resistance of each input while

maintaining constant total differential resistance, thereby adjusting the amplitude at each input but leaving the

differential swing constant. Phase correction, also considered capacitive balance correction, varies the capacitive

load at the ADC input, thereby correcting a phase imbalance by creating a bandwidth difference between the

analog inputs that minimally affects amplitude. This function is useful for correcting the balance of transformers

or filters that drive the ADC analog inputs. Figure 33 shows the measured HD2 resulting from an example 240-

MHz imbalanced signal input into the ADC14X250 device recorded over the available amplitude and phase

correction settings, demonstrating the optimization of HD2. Performance parameters in the Electrical

Characteristics: Dynamic Converter Performance are characterized with the amplitude and phase correction

settings in the default condition.

Figure 33. Gain and Phase Imbalance HD2 Optimization

8.3.2 Input Clock Divider

An input clock divider allows a high frequency clock signal to be distributed throughout the system and locally

divided down at the ADC device so that coupling of signals at common intermediate frequencies into other parts

of the system can be avoided. The frequency at the CLKIN input may be divided down to the sampling rate of the

ADC by factors of 1, 2, 4, or 8. Changing the clock divider setting initiates a JESD204 link re-initialization and

requires re-calibration of the ADC if the sampling rate is changed from the rate during the previous calibration.

8.3.3 SYSREF Offset Feature and Detection Gate

When the signal at the SYSREF input is not actively toggling periodically, the SYSREF signal is considered to be

in an idle state. The idle state is recommended at any time the ADC14X250 spurious performance must be

maximized. When the SYSREF signal is in the idle state for longer than 1 µs, an undesirable offset voltage may

build up across the AC coupling capacitors between the SYSREF transmitter and the ADC14X250 device input.

This offset voltage creates a signal threshold problem, requires a long time to dissipate, and therefore prevents

quick transition of the SYSREF signal out of the idle state. Two features are provided as a solution and are

shown in Figure 50, namely the SYSREF offset feature and SYSREF detection gate.

ADC14X250 Datasheet(PDF) 24 Page - Texas Instruments