ADC14X250 datasheet(55/69 Pages) TI1

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ADC14X250

(ADC)

BPF

DVGA

BPF

LNA

JESD204

SYSTEM

CLOCK

GENERATOR

FPGA /

ASIC

De-Modulator

BPF

DAC

DVGA

BPF

Modulator

BPF

ATT

BPF

DVGA

De-Modulator

ADC14X250

(ADC)

TRANSMITTER

RECEIVER

RF PLL

SYNTH

ADC14X250

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SLASE49 – DECEMBER 2015

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Typical Applications (continued)

(1)

These example design requirements do not represent the capabilities of the ADC14X250, rather the requirements are satisfied by the

ADC14X250.

Figure 56. High IF Receiver and Transmitter With Digital Pre-Distortion Path

9.2.1 Design Requirements

The following are example design requirements expected of the ADC in a typical high-IF, 100-MHz bandwidth

receiver, and is met by the ADC14X250 device:

Table 27. Example Design Requirements for a High-IF Application

Specification

Example Design Requirement(1)

ADC14X250 Capability

Sampling Rate

250-MSPS

Up to 250-MSPS

Input Bandwidth

> 400-MHz, 1-dB flatness

500-MHz, 1dB Bandwidth

Full Scale Range

< 2-Vpp-diff

1.7-Vpp-diff

Small Signal Noise Spectral Density

< –150-dBFS/Hz

–152.1-dBFS/Hz

Large Signal SNR

> 69-dBFS for a –3 dBFS, 240-MHz Input

70.1-dBFS for a –3 dBFS, 240-MHz Input

SFDR

> 80-dBFS for a –3 dBFS, 240-MHz input

87-dBFS for a –3 dBFS, 240-MHz input

HD2, HD3

< –80-dBFS for a –3 dBFS, 240-MHz input

–87-dBFS for a –3 dBFS, 240-MHz input

Next Largest SPUR

< –85-dBFS for a –3 dBFS, 240-MHz input

–92-dBFS for a –3 dBFS, 240-MHz input

Digital Interface

JESD204B interface, 1 lane/channel, < 10-

Gb/s bit rate

JESD204B subclass 1 interface, 1 lane, 5.0-Gb/s

bit rate

Configuration Interface

SPI configuration, 4-wire, 1.8-V logic, SCLK up

to 20-MHz

SPI configuration, 4-Wire, 1.8-V Logic, SCLK > 20-

MHz

Package Size

< 8 × 8 × 1 mm

5 × 5 × 0.8 mm

9.2.2 Design Procedure

The following procedure can be followed to design the ADC14X250 device into most applications:

•

Choose an appropriate ADC driver and analog input interface.

–

Optimize the signal chain gain leading up to the ADC to make use of the full ADC dynamic range.

–

Identify whether DC or AC coupling is required.

–

Determine the desired analog input interface, such as a bandpass filter or a transformer.

–

Use the provided input network models to design and verify the interface.

ADC14X250 Datasheet(PDF) 55 Page - Texas Instruments

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