ADC14X250 datasheet(26/69 Pages) TI1

26 / 69 page

ADC14X250

SLASE49 – DECEMBER 2015

www.ti.com

Product Folder Links: ADC14X250

Submit Documentation Feedback

Feature Description (continued)

Table 1 indicates the typical measured values for the de-emphasis range, where the de-emphasis value is

measured as the ratio (in units of [dB]) between the peak voltage after the signal transition to the settled voltage

value in one bit period. The data rate for this measurement is 1.2 Gb/s to allow settling of the de-emphasis

transient. Table 1 illustrates the actual de-emphasis value in terms of voltage attenuation and shows dependence

on the amplitude setting, but does not reflect the optimal amplitude setting (VOD) and de-emphasis setting

(DEM) for a particular lossy channel. Table 2 shows the amplitude of the differential signal swing during its

settled state after the transition transient. The measurement is performed at 1.2 Gb/s and the units are in

differential peak-to-peak mV.

Table 1. De-Emphasis Values (dB) for All VOD and DEM Configuration Settings

DEM

VOD

–0.2

–1.1

–2.2

–3.0

–4.3

–5.6

–8.5

–0.4

–1.7

–2.9

–3.8

–5.1

–6.5

–9.6

–0.7

–2.2

–3.5

–4.5

–5.9

–7.4

–10.4

–1.0

–2.8

–4.2

–5.2

–6.7

–8.1

–11.2

–1.4

–3.4

–4.9

–5.9

–7.4

–8.9

–12.1

–1.7

–3.9

–5.5

–6.5

–8.0

–9.5

–12.7

–2.1

–4.4

–6.0

–7.1

–8.6

–10.2

–13.4

–2.5

–4.9

–6.5

–7.6

–9.2

–10.7

–14.0

Table 2. Settled Differential Voltage Swing Values, VOD (mV-peak-peak) for All VOD and DEM

Configuration Settings

DEM

VOD

570

550

500

440

400

350

300

210

660

630

550

470

430

370

310

220

750

690

580

500

450

380

320

230

840

750

610

520

460

390

330

230

940

800

630

530

470

400

340

230

1020

840

650

550

480

410

340

240

1110

870

670

560

490

410

340

240

1200

900

680

570

500

420

350

240

8.3.6 ADC Core Calibration

After power-up, the ADC14X250 device detects that the supplies and clock are valid, waits for a power-up delay,

and then performs a calibration of the ADC core automatically. The power-up delay is 8.4 × 106 sampling clock

cycles or 33.6 ms at a 250-MSPS sampling rate. The calibration requires approximately 1.0 × 106 sampling clock

cycles.

If the system requires that the ADC14X250 input clock divider value (CLKDIV) is set to 2, 4, or 8, then ADC

calibration must be performed manually after CLKDIV has been set to the desired value. Manual calibration is

performed by changing to power down mode, returning to normal operation, and monitoring the CAL_DONE bit

in the JESD_STATUS register until calibration is complete. As an alternative to monitoring CAL_DONE, the

system may wait 1.5 × 106 sampling clock cycles until calibration is complete.

Re-calibration is not required across the supported operating temperature range to maintain functional

performance, but it is recommended for large changes in ambient temperature to maintain optimal dynamic

performance. Changing the sampling rate always requires re-calibration of the ADC core. For more information

about device modes, see Power-Down and Sleep Modes.

ADC14X250 Datasheet(PDF) 26 Page - Texas Instruments

ADC14X250 Datasheet(HTML) 26 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69

Datasheet Download

Link URL