ADC14X250 datasheet(56/69 Pages) TI1

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ADC14X250

SLASE49 – DECEMBER 2015

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Refer to the interface recommendations in Analog Input Considerations.

•

Determine the core sampling rate of the ADC.

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Must satisfy the bandwidth requirements of the application .

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Must also provide enough margin to prevent aliasing or to accommodate the transitions bands of an anti-

aliasing filter.

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Ensure the application initialization sequence properly handles ADC core calibration as described in ADC

Core Calibration.

•

Determine the system latency requirements.

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Total allowable latency through the ADC and JESD204B link.

–

Is the system tolerant of latency variation over time or conditions or between power cycles?

•

Determine the desired JESD204B link configuration as discussed in JESD204B Supported Features.

–

Based on the system latency requirements, determine whether deterministic latency is required across the

JESD204B link.

–

Choose the number of frames per multi-frame, K.

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Choose whether scrambling is desired.

•

Choose an appropriate clock generator, CLKIN interface, and SYSREF interface.

–

Determine the system clock distribution scheme and the clock frequencies for the CLKIN and SYSREF

inputs.

–

Determine the allowable amount of sampling clock phase noise in the system and then select a CLKIN

edge rate that satisfies this requirement as discussed in Clock Noise and Edge Rate.

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Choose an appropriate CLKIN interface as discussed in Driving the CLKIN+ and CLKIN– Input.

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Based on the latency requirements, determine whether SYSREF must meet setup and hold requirements

relative to CLKIN.

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Choose the SYSREF signal type as discussed in SYSREF Signaling.

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Choose an appropriate SYSREF interface as discussed in Driving the SYSREF Input.

–

Choose a CLKIN and SYSREF clock generator based on the above requirements. The signals need come

from the same generator in some cases.

–

Determine what clock idle modes are supported by the SYSREF clock generator and choose the

appropriate setting for the SYSREF Offset feature as discussed in Effectively Using the SYSREF Offset

and Detection Gate Features .

•

Design the SYNCb interface as discussed in Driving the SYNCb Input.

•

Choose appropriate configurations for the output serial data interface.

–

Design the serial lane interface according to Output Serial-Lane Interface.

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Choose the required PCB materials, keeping in mind the desired rate of the serial lanes.

–

Characterize the signal lane channels the connect the ADC serial output transmitters to the receiving

device either through simulation or bench characterization.

–

Optimize the VOD and DEM parameters to achieve the required signal integrity according to Voltage

Swing and De-Emphasis Optimization.

•

Design the SPI bus interface.

–

Verify the electrical and functional compatibility of the ADC SPI with the SPI controller.

–

Interface the ADC to the SPI bus according to SPI.

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Ensure that the application initialization sequence properly configures the output SDO voltage before the

first read command.

•

Design the power supply architecture and de-coupling.

–

Choose appropriate power supply and supply filtering devices to provide stable, low-noise supplies as

described in Power Supply Design.

–

Design the capacitive de-coupling around the ADC, also described in Power Supply Design, while paying

close attention to placing the capacitors as close to the device as possible.

–

Time the power architecture to satisfy the power sequence requirements described in Power Supply

Design.

•

Ensure that the application initialization sequence satisfies the JESD204B link initialization requirements

described in JESD204B Link Initialization.

ADC14X250 Datasheet(PDF) 56 Page - Texas Instruments

ADC14X250 Datasheet(HTML) 56 Page - Texas Instruments

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