 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ADC14X250 Datasheet(PDF) 38 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
ADC14X250 Datasheet(HTML) 38 Page - Texas Instruments |
|
|
38 / 69 page  38 ADC14X250 SLASE49 – DECEMBER 2015 www.ti.com Product Folder Links: ADC14X250 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated 8.5.1.14 JESD_CTRL2 (JESD Configuration Control 2), [Address: 0x0061], [Default: 0x00] Table 20. JESD_CTRL2 (JESD Configuration Control 2), [Address: 0x0061], [Default: 0x00] Note: Before altering any parameters in this register, one must set JESD_EN = 0. Changing parameters while JESD_EN = 1 is not supported. Bit Field Type Reset Description [7] SYNC_SEL Read or write 0 SYNCb Signal MUX Select 0 : The internal SYNCb signal is routed from the SYNCb+/- pins (default) 1 : The internal SYNCb signal is routed from the JSYNC_N register field (SYNCb over SPI) [6] JSYNC_N Read or write 0 SYNCb Over SPI Control 0 : The internal SYNCb signal as asserted, indicating a JESD204 link synchronization request (default) 1 : The internal SYNCb signal is de-asserted, indicating JESD204 link synchronization is not being requested Note: JSYNC_N controls the internal SYNCb signal only when SYNC_SEL = 1. When SYNC_SEL = 0, this register field is ignored. [7:4] Reserved Read or write 00 Reserved. Must be written as 00. [3:0] JESD_TEST_ MODES[3:0] Read or write 0000 JESD204B test modes. 0000 : Test mode disabled. Normal operation (default) 0001 : PRBS7 test mode 0010 : PRBS15 test mode 0011 : PRBS23 test mode 0100 : RESERVED 0101 : ILA test mode 0110 : Ramp test mode 0111 : K28.5 test mode 1000 : D21.5 test mode 1001: Logic low test mode (serial outputs held low) 1010: Logic high test mode (serial outputs held high) 1011 – 1111 : Reserved Note: • JESD_EN must be set to 0 before altering this field. 8.5.1.15 JESD_RSTEP (JESD Ramp Pattern Step), [Addresses: 0x0063, 0x0062], [Default: 0x00, 0x01] Table 21. JESD_RSTEP (JESD Ramp Pattern Step), [Addresses: 0x0063, 0x0062], [Default: 0x00, 0x01] Bit Field Type Reset Description 0x0062[7:0] JESD_RSTEP [7:0] Read or write 0x01 JESD204B ramp test mode step 0x0063[7:0] JESD_RSTEP [15:8] Read or write 0x00 The binary value JESD_RSTEP[15:0] corresponds to the step of the ramp mode step. A value of 0x0000 is not allowed. Note: • JESD_EN must be set to 0 before altering this field. 8.5.1.16 JESD_STATUS (JESD Link Status), [Address: 0x006C], [Default: N/A] Table 22. JESD_STATUS (JESD Link Status), [Address: 0x006C], [Default: N/A] Bit Field Type Reset Description [7] Reserved Read N/A Reserved. [6] LINK Read N/A JESD204B link status This bit is set when synchronization is finished, transmission of the ILA sequence is complete, and valid data is being transmitted. 0 : Link not established 1 : Link established and valid data transmitted |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
