ADC14X250 datasheet(60/69 Pages) TI1

60 / 69 page

0.007''

0.004''

0.007''

L1 ± SIG

L2 ± GND

L3 ± PWR/SIG

L6 ± SIG

L5 ± GND

L4 ± PWR

1 oz. Copper on L2-5, 2 oz. Copper on L1, L6

100 Differential Signaling on SIG Layers

Low loss dielectric adjacent very high speed trace layers

0.0625''

ADC14X250

SLASE49 – DECEMBER 2015

www.ti.com

Product Folder Links: ADC14X250

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11 Layout

11.1 Layout Guidelines

•

The design of the PCB is critical to achieve the full performance of the ADC14X250 device. Defining the PCB

stackup should be the first step in the board design. Experience has shown that at least 6 layers are required

to adequately route all required signals to and from the device. Each signal routing layer must have an

adjacent solid ground plane to control signal return paths to have minimal loop areas and to achieve

controlled impedances for microstrip and stripline routing. Power planes must also have adjacent solid ground

planes to control supply return paths. Minimizing the spacing between supply and ground planes improves

performance by increasing the distributed decoupling. The recommended stack-up for a 6-layer board design

is shown in Figure 59.

•

Although the ADC14X250 device consists of both analog and digital circuitry, TI highly recommends solid

ground planes that encompass the device and its input and output signal paths. TI does not recommend split

ground planes that divide the analog and digital portions of the device. Split ground planes may improve

performance if a nearby, noisy, digital device is corrupting the ground reference of the analog signal path.

When split ground planes are employed, one must carefully control the supply return paths and keep the

paths on top of their respective ground reference planes.

•

Quality analog input signal and clock signal path layout is required for full dynamic performance. Symmetry of

the differential signal paths and discrete components in the path is mandatory and symmetrical shunt-oriented

components should have a common grounding via. The high frequency requirements of the input and clock

signal paths necessitate using differential routing with controlled impedances and minimizing signal path

stubs (including vias) when possible.

•

Coupling onto or between the clock and input signal paths must be avoided using any isolation techniques

available including distance isolation, orientation planning to prevent field coupling of components like

inductors and transformers, and providing well coupled reference planes. Via stitching around the clock signal

path and the input analog signal path provides a quiet ground reference for the critical signal paths and

reduces noise coupling onto these paths. Sensitive signal traces must not cross other signal traces or power

routing on adjacent PCB layers, rather a ground plane must separate the traces. If necessary, the traces

should cross at 90° angles to minimize crosstalk.

•

The substrate dielectric materials of the PCB are largely influenced by the speed and length of the high speed

serial lanes. The affordable and common FR4 variety may not offer the consistency or loss to support very

high speed transmission (> 5 Gb/s) and long lengths (> 4 inch). Although the VOD and DEM features are

available to improve the signal integrity of the serial lanes, some of the highest performing applications may

still require special dielectric materials such as Rogers 4350B or Panasonic Megtron 6.

•

Coupling of ambient signals into the signal path is reduced by providing quiet, close reference planes and by

maintaining signal path symmetry to ensure the coupled noise is common-mode. Faraday caging may be

used in very noisy environments and high dynamic range applications to isolate the signal path.

Figure 59. Recommended PCB Layer Stack-Up for a Six-Layer Board

ADC14X250 Datasheet(PDF) 60 Page - Texas Instruments

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