ADC14X250 datasheet(31/69 Pages) TI1

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SCLK

CSB

R/W

A14

A13

A12

A11

A10

(MSB)

(LSB)

COMMAND FIELD

DATA FIELD

Address (15-bits)

Write DATA (8-bits)

SDI

SDO

Hi-Z

(MSB)

(LSB)

Read DATA (8-bits)

Single Access Cycle

(MSB)

(LSB)

R=1

W=0

ADC14X250

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SLASE49 – DECEMBER 2015

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8.3.12 Sync~ Signal Selection

The JESD204B sync~ signal can be directed to the internal JESD204B core block via two different input paths:

via the external pins or SPI. The selection MUX is controlled using the SYNC_SEL register field and sync~

control is performed using the JSYNC_N register field via SPI . By default, the signal is routed from the external

SYNCb+/- pins and writes to the JSYNC_N register field are ignored.

Optionally, the signal may be routed via SPI by setting the register field SYNC_SEL = 1. In this mode, signals at

the external SYNCb+/- pins are ignored and the sync~ signal is written to the JSYNC_N register field.

8.3.13 SPI

The SPI allows access to the internal configuration registers of the ADC through read and write commands to a

specific address. The interface protocol has a 1-bit command, 15-bit address word and 8-bit data word as shown

in Figure 38. A read or write command is 24 bits in total, starting with the read or write command bit where 0

indicates a write command and 1 indicates a read command. The read or write command bit is clocked into the

device on the first rising edge of SCLK after CSb is asserted to 0. During a write command, the 15-bit address

and 8-bit data values follow the read or write bit MSB-first and are latched on the rising edge of SCLK. During a

read command, the SDO output is enabled shortly after the 16th rising edge of SCLK and outputs the read value

MSB first before the SDO output is returned to a high impedance state. The read or write command is completed

on the SCLK rising edge on which the data word’s LSB is latched. CSb may be de-asserted to 1 after the LSB is

latched into the device.

The SPI allows command streaming where multiple commands are made without de-asserting CSb in-between

commands. The commands in the stream must be of similar types, either read or write. Each subsequent

command applies to the register address adjacent to the register accessed in the previous command. The

address order can be configured as either ascending or descending. Command streaming is accomplished by

immediately following a completed command with another set of 8 rising edges of SCLK without de-asserting

CSb. During a write command, an 8-bit data word is input on the SDI input for each subsequent set of SCLK

edges. During a read command, data is output from SDO for each subsequent set of SCLK edges. Each

subsequent command is considered finished after the 8th rising edge of SCLK. De-asserting CSb aborts an

incomplete command.

The SDO output is high impedance at all times other than during the final portion of a read command. During the

time that the SDO output is active, the logic level is determined by a configuration register. The SPI output logic

level must be properly configured after power up and before making a read command to prevent damaging the

receiving device or any other device connected to the SPI bus. Until the SPI_CFG register is properly configured,

voltages on the SDO output may be as high as the VA3.0 supply during a read command. The default state of

SDO is to output 1.8 V logic levels during a read command. The SDI, SCLK, and CSB pins are all 1.2-V to 3-V

logic compatible.

Figure 38. Serial Interface Protocol

ADC14X250 Datasheet(PDF) 31 Page - Texas Instruments

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