ADC14X250 datasheet(28/69 Pages) TI1

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ADC14X250

SLASE49 – DECEMBER 2015

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These parameters have a binary-value-minus-1 encoding applied before being mapped into the link configuration octets. For example, F

= 1 is encoded as 0.

8.3.9.3 ILA Information

Table 4 summarizes the information transmitted during the initial lane alignment (ILA) sequence. Mapping of

these parameters into the data stream is described in the JESD204B standard.

Table 4. Configuration of the JESD204B Serial-Data Receiver

Paramet

Description

Logical Value

Encoded Value

ADJCNT

DAC LMFC adjustment

ADJDIR

DAC LMFC adjustment direction

BID

Bank ID

Number of control words per frame clock period

per link

Number of control bits per sample

DID

Device identification number

Number of octets per frame (per lane)(1)

High-density format

JESDV

JESD204 version

Number of frames per multi-frame(1)

Set by register as 9 to 32

8 to 31

Number of lanes per link(1)

LID

Lane identification number

Number of converters per device(1)

Converter resolution (1)

N’

Total number of bits per sample(1)

PHADJ

Phase adjustment request to DAC

Number of samples per converter per frame

cycle(1)

SCR

Scrambling enabled

Set by register as 0

(disabled) or 1

0 or 1

SUBCLA

SSV

Device subclass version

RES1

Reserved field 1

RES2

Reserved field 2

FCHK

Checksum

34 + (K-1) + SCR

Scrambling of the output serial data is supported and conforms to the JESD204B standard. Scrambling is

disabled by default, but may be enabled via the SPI. When scrambling is enabled, the ADC14X250 device

supports the early synchronization option by the receiver during the ILA sequence, although the ILA sequence

data is never scrambled.

8.3.10 Test Pattern Sequences

The SPI may enable the following test pattern sequences. Short- and long-transport layer, RPAT, and JSPAT

sequences are not supported.

Table 5. Supported Test Pattern Sequences

Test Pattern

Description

Common Purpose

D21.5

Alternating 1 and 0 pattern (101010...)

Jitter or system debug

K28.5

Continuous K28.5 symbols

System debug

Repeated ILA

ILA repeats indefinitely

System debug

Ramp

After ILA, a sample ramp is transmitted with programmable

step. The 16-bit output word fully spans both octets that

compose a sample.

System debug and transport layer verification

ADC14X250 Datasheet(PDF) 28 Page - Texas Instruments

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