ADC14X250 datasheet(40/69 Pages) TI1

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ADC14X250

SLASE49 – DECEMBER 2015

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Analog Input Considerations

9.1.1.1 Differential Analog Inputs and Full Scale Range

The ADC14X250 device has a single channel with a pair of analog signal input pins: VIN+, VIN

−. VIN, the input

differential signal for a channel, is defined as VIN = (VIN+) – (VIN

−). Table 23 shows the expected input signal

range when the differential signal swings about the input common mode, VCM. The full-scale differential peak-to-

peak input range is equal to twice the internal reference voltage, VREF. Nominally, the full scale range is 1.7

Vpp-diff, therefore the maximum peak-to-peak single-ended voltage is 0.85 Vpp at each of the VIN+ and VIN

−

pins.

The single-ended signals must be opposite in polarity relative to the VCM voltage to provide a purely differential

signal, otherwise the common-mode component may be rejected by the ADC input. Table 23 indicates the input

to output relationship of the ADC14X250 device where VREF = 0.85 V. Differential signals with amplitude or phase

imbalances result in lower system performance compared to perfectly balanced signals. Imbalances in signal

path circuits lead to differential-to-common-mode signal conversion and differential signal amplitude loss as

shown in Figure 39. This deviation or imbalance directly causes a reduction in the signal amplitude and may also

lead to distortion, particularly even order harmonic distortion, as the signal propagates through the signal path.

The differential imbalance correction feature of the ADC14X250 device helps to correct amplitude or phase

errors in the signal.

Table 23. Mapping of the Analog Input Full Scale Range to Digital Codes

VIN+

VIN–

2s Complement Output

Binary Output

Note

VCM – VREF / 2

VCM + VREF / 2

10 0000 0000 0000

00 0000 0000 0000

Negative full-scale

VCM – VREF / 4

VCM + VREF / 4

11 0000 0000 0000

01 0000 0000 0000

VCM

00 0000 0000 0000

10 0000 0000 0000

Mid-scale

VCM + VREF / 4

VCM – VREF / 4

01 0000 0000 0000

11 0000 0000 0000

VCM + VREF / 2

VCM – VREF / 2

01 1111 1111 1111

11 1111 1111 1111

Positive full-scale

ADC14X250 Datasheet(PDF) 40 Page - Texas Instruments

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