ADC14X250 datasheet(47/69 Pages) TI1

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CLKIN Zero Crossing Edge Rate [V/ns]

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C001

ADC14X250

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SLASE49 – DECEMBER 2015

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9.1.2.2 Clock Noise and Edge Rate

Noise added to the sampling clock path of the ADC degrades the SNR performance of the system. This noise

may include broadband noise added by the ADC clock receiver inside the ADC device but may also include

broadband and in-close phase noise added by the clock generator and any other devices leading to the CLKIN

input. The theoretical SNR performance limit of the ADC14X250 device as a result of clock noise for a given

input frequency is shown in Figure 48 for a full scale input signal and different values of total jitter.

Figure 48. SNR Limit Due to Jitter of Sampling Clock With a Full-Scale Input Signal

The differential clock receiver of the ADC14X250 device has a very-low noise floor and wide bandwidth. The

wide band clock noise of the receiver, also referred to as the additive jitter, modulates the sampling instant and

adds the noise to the signal. At the sampling instant, the added broadband noise appears in the first Nyquist

zone at the ADC output to degrade the noise performance. Minimizing the additive jitter requires a sampling

clock with a steep edge rate at the zero crossing. Reduced edge rate increases the additive jitter. For clock

signals with a differential swing of 100 mV or greater, the additive clock Figure 49 shows the SNR performance

of the ADC14X250 device for a range of clock transition slopes.

Figure 49. SNR vs Input Clock Edge Rate (–3 dBFS Input)

Noise added to the sampling clock by devices leading up to the ADC clock input also directly affects the noise

performance of the system. In-close phase noise is typically dominated by the performance of the clock

reference and phase-locked loop (PLL) that generates the clock and limits the sensitivity of the sampling system

at desired frequencies offset 100 Hz to 10 MHz away from a large blocking signal. Little can be done to improve

the in-close phase noise performance without the use of an additional PLL. Broadband noise added in the clock

path limits the sensitivity of the whole spectrum and may be improved by using lower noise devices or by

inserting a band-pass filter (BPF) with a narrow pass band and low insertion loss to the clock input signal path.

Adding a BPF limits the transition rate of the clock, thereby creating a trade-off between the additive jitter added

by the ADC clock receiver and the broadband noise added by the devices that drive the clock input.

Additional noise may couple to the clock path through power supplies. Take care to provide a very-low noise

power supply and isolated supply return path to minimize noise added to the supply. Spurious noise added to the

clock path results in symmetrical, modulated spurs around large input signals. These spurs have a constant

magnitude in units of dB relative to the input signal amplitude or carrier, [dBc].

ADC14X250 Datasheet(PDF) 47 Page - Texas Instruments

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