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ADC14X250 Datasheet(PDF) 35 Page - Texas Instruments |
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ADC14X250 Datasheet(HTML) 35 Page - Texas Instruments |
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35 / 69 page  35 ADC14X250 www.ti.com SLASE49 – DECEMBER 2015 Product Folder Links: ADC14X250 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated 8.5.1.6 VENDOR_ID, [Address: 0x000D, 0x000C], [Default: 0x04, 0x51] Table 12. VENDOR_ID, [Address: 0x000D, 0x000C], [Default: 0x04, 0x51] Bit Field Type Reset Description 0x000C[7:0] VENDOR_ID [7:0] Read 0x51 Vendor ID. Texas Instruments vendor ID is 0x0451. 0x000D[7:0] VENDOR_ID [15:8] Read 0x04 8.5.1.7 SPI_CFG, [Address: 0x0010], [Default: 0x01] Table 13. SPI_CFG, [Address: 0x0010], [Default: 0x01] Bit Field Type Reset Description [7:2] Reserved Read or write 000000 Reserved and must be written with 000000. [1:0] VSPI Read or write 01 SPI logic level controls the SDO output logic level. 00 : 1.2 V 01 : 1.8 V (default) 10 : 2.5 V 11 : 3.0 V This register must be configured (written) before making a read command on the SPI bus if the logic level is different that the VSPI setting. The SPI inputs (SDI, SCLK, and CSb) are compatible with logic levels ranging from 1.2 to 3.0 V. 8.5.1.8 OM1 (Operational Mode 1), [Address: 0x0012], [Default: 0x81] Table 14. OM1 (Operational Mode 1), [Address: 0x0012], [Default: 0x81] Bit Field Type Reset Description [7] DF Read or write 1 Output data format 0 : Offset binary 1 : Signed 2s complement (default) [6:5] Reserved Read or write 00 Reserved and must be written with 00. [4:3] IDLE[1:0] Read or write 00 SYSREF idle state offset configuration. 00 : No offset applied (default) 01 : SYSREF idles low (de-asserted) with –400-mV offset 10 : SYSREF idles high (asserted) with +400-mV offset 11 : Reserved [2] SYS_EN Read or write 0 SYSREF detection gate enable 0 : SYSREF gate is disabled; (input is ignored, default) 1 : SYSREF gate is enabled [1:0] Reserved[1:0] Read or write 01 Reserved. Must be written with 01. 8.5.1.9 OM2 (Operational Mode 2), [Address: 0x0013], [Default: 0x20] Table 15. OM2 (Operational Mode 2), [Address: 0x0013], [Default: 0x20] Bit Field Type Reset Description [7:5] Reserved Read or write 001 Reserved and must be written with 001. [4:3] CLKDIV[1:0] Read or write 00 Clock divider ratio. Sets the value of the clock divide factor, CLKDIV 00 : Divide by 1, CLKDIV = 1 (default) 01 : Divide by 2, CLKDIV = 2 10 : Divide by 4, CLKDIV = 4 11 : Divide by 8, CLKDIV = 8 [2:0] Reserved Read or write 000 Reserved. Must be written with 000. |
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