ADC14X250 datasheet(27/69 Pages) TI1

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L=1

S=1

F=2

Octet 0

(MSB)

(LSB)

Octet 1

(MSB)

(LSB)

D[13:0] = Sampled Data

0 = Zero padded bit

Lane

D[0]

D[8]

D[1]

D[2]

D[3]

D[4]

D[5]

D[6]

D[7]

N=16

CS=0

1¶=16

D[13] D[12] D[11] D[10] D[9]

ADC14X250

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The ADC14X250 supports most subclass 0 requirements, but is not strictly subclass compliant.

8.3.7 Data Format

Data may be output in the serial stream as 2’s complement format by default or optionally as offset binary. This

formatting is configured through the SPI and is performed in the data path prior to JESD204B data framing,

scrambling and 8b/10b encoding.

8.3.8 JESD204B Supported Features

The ADC14X250 device supports a feature set of the JESD204B standard targeted to its intended applications

but does not implement all the flexibility of the standard. Table 3 summarizes the level of feature support.

Table 3. ADC14X250 Feature Support for the JESD204B Serial Interface

Feature

Supported

Not Supported

Subclass

•

Subclass 1

•

Subclass 0(1), 2

Device Clock

(CLKIN) and

SYSREF

•

AC coupled CLKIN and SYSREF

•

DC coupled CLKIN and SYSREF (special cases)

•

Periodic, Pulsed Periodic and One-Shot SYSREF

Latency

•

Deterministic

latency

supported

for

subclass

implementations using standard SYSREF signal

•

Deterministic latency not supported for non-

standard implementations

Electrical layer

features

•

LV-OIF-11G-SR interface and performance

•

AC coupled serial lanes

•

TX lane polarity inversion

•

DC coupled serial lanes

Transport layer

features and

configuration

•

L = 1

•

K configuration

•

Scrambling

•

F, S, and HD configuration depends on L and is

not independently configurable

•

M, N, N’, CS, CF configuration

•

Idle link mode

•

Short and Long transport layer test patterns

Data link layer

features

•

8b/10b encoding

•

Lane synchronization

•

D21.5, K28.5, ILA, PRBS7, PRBS15, PRBS23, Ramp test

sequences

•

RPAT/JSPAT test sequences

8.3.9 Transport Layer Configuration

The transport layer features supported by the ADC14X250 device are a subset of possible features described in

the JESD204B standard. The configuration options are intentionally simplified to provide the lowest power and

most easy-to-use solution.

8.3.9.1 Lane Configuration

The ADC14X250 outputs all digital data on a single JESD204B serial lane. The serial-data lane transmits at 20

times the sampling rate. A 250 MSPS sampling rate corresponds to a 5.0 Gb/s per lane rate.

8.3.9.2 Frame Format

The format of the data arranged in a frame is fixed. The octets per frame (F), samples per frame (S), and high-

density mode (HD) parameters are not independently configurable. The N, N’, CS, CF, M, and HD parameters

are fixed and not configurable. Figure 35 shows the data format.

Figure 35. Transport Layer Definitions for the Supported-Lane Configurations

ADC14X250 Datasheet(PDF) 27 Page - Texas Instruments

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