Electronic Components Datasheet Search
  English  ▼

X  

ADC14X250 Datasheet(PDF) 62 Page - Texas Instruments

Click here to check the latest version.
Part # ADC14X250
Description  MSPS Single Channel ADC
PDF  69 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC14X250 Datasheet(HTML) 62 Page - Texas Instruments

Back Button ADC14X250 Datasheet HTML 58Page - Texas Instruments ADC14X250 Datasheet HTML 59Page - Texas Instruments ADC14X250 Datasheet HTML 60Page - Texas Instruments ADC14X250 Datasheet HTML 61Page - Texas Instruments ADC14X250 Datasheet HTML 62Page - Texas Instruments ADC14X250 Datasheet HTML 63Page - Texas Instruments ADC14X250 Datasheet HTML 64Page - Texas Instruments ADC14X250 Datasheet HTML 65Page - Texas Instruments ADC14X250 Datasheet HTML 66Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 62 / 69 page
background image
62
ADC14X250
SLASE49 – DECEMBER 2015
www.ti.com
Product Folder Links: ADC14X250
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
12 Device and Documentation Support
12.1 Device Support
12.1.1 Related Documentation
See the Isolation Glossary (SLLA353)
12.1.1.1 Specification Definitions
3-dB BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental deviates 3 dB
from its low frequency value relative to the differential voltage signal applied at the device input
pins.
APERTURE DELAY is the time delay between the rising edge of the clock until the input signal is acquired or
held for conversion.
APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample.
CLOCK DUTY CYCLE is the ratio of the time during one cycle that a repetitive digital waveform is high to the
total time of one period. The specification here refers to the ADC clock input signal.
COMMON MODE VOLTAGE (VCM) is the common DC voltage applied to both terminals of the ADC differential
input.
COMMON MODE REJECTION RATIO (CMRR) is the ratio of the magnitude of the single-tone spur in the
sampled spectrum (referred to the ADC analog input as a peak voltage quantity) to the peak
voltage swing of a sinusoid simultaneously incident on the positive and negative terminals of a
differential analog input as a common-mode signal from which the spur generated. CMRR is
typically expressed in decibels [dB].
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
least significant bit (LSB)
GAIN VARIATION is the expected standard deviation in the gain of the converter from an applied voltage to
output codes between parts or between channels.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a best-fit straight
line. The deviation of any given code from this straight line is measured from the center of that code
value.
INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two
sinusoidal frequencies being applied to the ADC input at the same time. It quantifies the power of
the largest intermodulation product adjacent to the input tones, expressed in dBFS.
LEAST SIGNIFICANT BIT (LSB) is the bit that has the smallest value or weight of all bits. This value is VFS / 2
n,
where VFSis the full scale input voltage and n is the ADC resolution in bits.
MISSING CODES are those output codes that do not appear at the ADC outputs. The ADC14X250 device is
specified not to have missing codes.
MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight. Its value is one half of full scale.
OFFSET ERROR is the difference between the two input voltages (VIN+ – VIN–) required to cause a transition
from code 8191LSB and 8192LSB with offset binary data format.
POWER SUPPLY SENSITIVITY is a measure of the sensitivity of the power supplies to noise. In this
specification, a supply is modulated with a 100-mV, 500-kHz sinusoid and the resulting spurs in the
spectrum are measured. The sensitivity is expressed relative to the power of a possible full-scale
sinusoid [dBFS].
SAMPLE-TO-SERIAL OUT (S2SO) LATENCY is the number of frame clock cycles between initiation of
conversion and the time when the first bit of serial data for that sample is present at the output
driver. This latency is not specified to be deterministic.
SAMPLE-TO-PARALLEL OUT (S2PO) LATENCY is the number of frame clock cycles between initiation of
conversion and the time when the parallel sample data is available at the output of the receiver’s



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com