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DP8344 Datasheet(PDF) 28 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # DP8344
Description  Biphase Communications Processor?좦CP
PDF  184 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP8344 Datasheet(HTML) 28 Page - National Semiconductor (TI)

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20 CPU Description (Continued)
22 CPU FUNCTIONAL DESCRIPTION
221 ALU
The BCP provides a full function high speed 8-bit Arithmetic
Logic Unit (ALU) with full carry look ahead signed arithme-
tic and overflow decision capabilities The ALU can perform
six arithmetic nine logic one rotate and two shift operations
on binary data Full access is provided to all CPU registers
as both source and destination operands and using the in-
direct addressing mode results may be placed directly into
data memory All operations which have an internal destina-
tion (register addressing) are completed in two (2) T-states
External destination operations (indirect addressing to data
memory) complete in three (3) T-states
Arithmetic operations include addition with or without carry
and subtraction with or without borrow (represented by car-
ry) Subtractions are performed using 2’s complement addi-
tion to accommodate signed operands The subtrahend is
converted to its 2’s complement equivalent by the ALU and
then added to the minuend The result is left in 2’s comple-
ment form
The remaining ALU operations include full logic shift and
rotate operations The logic functions include Complement
AND
OR
Exclusive-OR
Compare and Bit Test
Zero
through seven bit right and left shift operations are provided
along with a zero through seven bit right rotate operation
Note that the shift and rotate operations may only be per-
formed on a register which is both the source and destina-
tion (See the Instruction Set Overview section for detailed
descriptions of these operations)
The BCP ALU provides the programmer with four instruction
result status bits for conditional operations These bits
(known as condition code flags) indicate the status (or con-
dition) of the destination byte produced by certain instruc-
tions Not all instructions have an affect on every status flag
(See the Instruction Set Reference section for the specific
details on what status flags a given instruction affects)
These flags are held in the Condition Code Register
CCR
see
Figure 2-7
76543210
TO
RR
RW
BIRQ
N
V
C
Z
where
N e Negative
C e Carry
V e Overflow
Z e Zero
FIGURE 2-7 Condition Code Register ALU Flags
If an instruction is documented as affecting a given flag
then the flags are set (to 1) or cleared (to 0) under the
following conditions
N
The Negative flag is set if the most significant bit
(MSB) of the result is one (1) otherwise it is cleared
This flag represents the sign of the result if it is inter-
preted as a 2’s complement number
C
The Carry flag is set if
a) An addition operation generates a carry see
Fig-
ure 2-8a
b) A subtract or compare operation generates a bor-
row see
Figure 2-8b
c) The last bit shifted out during a shift operation (in
either direction) is a one (1) see
Figure 2-9
d) The last bit rotated by the rotate operation is a one
(1) see
Figure 2-10
In all other conditions C is cleared
V
Overflow is set whenever the result of an arithmetic or
compare operation on signed operands is not repre-
sentable by the operand size thereby producing an
incorrect result For example the addition of the two
signed negative numbers in
Figure 2-8a would set V
since the correct representation of the result both
sign and magnitude is not possible in 8 bits On the
other hand in
Figure 2-8b and 2-8c
V would be
cleared because the results are correctly represented
in both sign and magnitude It is important to remem-
ber that Overflow is only meaningful in signed arith-
metic and that it is the programmer’s responsibility to
determine if a given operation involves signed or un-
signed values
Z
The Zero flag is set only when an operation produces
an all bits cleared result (ie a zero) In all other con-
ditions Z is cleared
11101010
10111010
11011100
a
10001100
b
11000100
a
01100011
1
w 01110110
1
x 11110110
1
w 00111111
C e 1
C e 1
C e 1
V e 1
V e 0
V e 0
(a)
(b)
(c)
FIGURE 28 Carry and Overflow Calculations
TLF9336 – D3
FIGURE 2-9 Shifts’ Effect on Carry
TLF9336 – D4
FIGURE 2-10 Rotate’s Effect on Carry
28



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