DP8344 datasheet(22/184 Pages) NSC

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20 CPU Description (Continued)

Integer Arithmetic Instructions

The integer arithmetic instructions operate on 8-bit signed

(two’s complement) binary numbers Two arithmetic func-

tions are supported Add and Subtract Three versions of

the Add and Subtract instructions exist operand g accumu-

lator operand g accumulator g carry and immediate oper-

and g operand The first two versions support both the reg-

ister and indexed addressing modes for the destination op-

erand These two versions also allow the specification of a

separate register or data address for the destination oper-

and so that the sources may retain their integrity (ie true

three-operand instructions) Note that the currently active

‘‘B’’ register bank selects which accumulator is used in

these instructions The third version immediate operand g

operand only supports the register addressing mode for the

destination operand with the register as both a source and

the destination Table 2-6 lists the integer arithmetic instruc-

tions along with their variations

Logic Instructions

The logic instructions operate on 8-bit binary data A full set

of logic functions is supported by the BCP AND OR eXclu-

sive OR and Complement All the logic functions except

complement allow either an immediate operand or the cur-

rently active accumulator as an implied operand Comple-

ment only allows one register operand which is both the

source and destination The other logic instructions include

the following addressing modes register indexed and im-

mediate As with the integer arithmetic instructions the in-

tegrity of the sources may be maintained by specifying a

destination register which is different from the source Table

2-7 lists all the logic instructions

TABLE 2-6 Integer Arithmetic Instructions

Syntax

Instruction Operation

Addressing Modes

ADD

n rsd

x register

Immediate Limited Register

ADDA

Rs Rd

Rs a accumulator

x Rd

ADDA

Rs mlr

Rs a accumulator

x data memory

ADCA

Rs Rd

Rs a accumulator a carry

x Rd

ADCA

Rs mlr

Rs a accumulator a carry

x data memory

SUB

n rsd

x register

Immediate Limited Register

SUBA

Rs Rd

Rs b accumulator

x Rd

SUBA

Rs mlr

Rs b accumulator

x data memory

SBCA

Rs Rd

Rs b accumulator b carry

x Rd

SBCA

Rs mlr

Rs b accumulator b carry

x data memory

TABLE 2-7 Logic Instructions

Syntax

Instruction Operation

Addressing Modes

AND

n rsd

x register

Immediate Limited Register

ANDA

Rs Rd

accumulator

x Rd

ANDA

Rs mlr

accumulator

x data memory

n rsd

l n x register

Immediate Limited Register

ORA

Rs Rd

l accumulator x Rd

ORA

Rs mlr

l accumulator x data memory

XOR

n rsd

x register

Immediate Limited Register

XORA

Rs Rd

Rs Z accumulator

x Rd

XORA

Rs mlr

Rs Z accumulator

x data memory

CPL

Rsd

x register

Note

logical AND operation

l e logical OR operation

Z e

logical exclusive OR operation

r e one’s complement

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