DP8344 datasheet(74/184 Pages) NSC

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40 Remote Interface and Arbitration System (RIAS) (Continued)

The last possible Memory Selection is Instruction Memory

MS1–0 e 01 The two possible next states for an IMEM

access depend on if RASM is expecting the low byte or high

byte Instruction words are accessed low byte then high

byte and RASM powers up expecting the low Instruction

byte The internal flag that keeps track of the next expected

Instruction byte is called the High Instruction Byte flag (HIB)

If HIB is low the next state is RSD5 and the low instruction

byte is MUXed to the AD bus If HIB is high the high instruc-

tion byte is MUXed to AD and RSD6 is entered An IMEM

access like a DMEM access is subject to wait states and

these states will be looped on until all programmed instruc-

tion memory wait states have been inserted

Note

Resetting the BCP will reset HIB (ie

HIB e 0) Writing 01 to the

Memory Select bits in RIC (ie

MS1–0 e 01 pointing to IMEM)

will also force HIB to zero This way the instruction word boundary

can be reset without resetting the BCP

After all of the programmed wait states are inserted in the

RSD states more wait states may be added by asserting

WAIT low a half T-state before the end of the last pro-

grammed wait state If there are no programmed wait

states WAIT must be asserted low a half T-state before the

end of RSD to add wait states If WAIT remains low the

remote access is extended indefinitely All the RSD states

move to their corresponding RSE states on the CPU-CLK

after the programmed wait state conditions are met and

WAIT is high The RSE states are looped upon until RAE

REM-RD is deasserted LCL remains high in all RSE states

and A remains in TRI-STATE AD will also stay in TRI-

STATE if the access was to DMEM XACK is taken back

high to indicate that data is now valid on the read If XACK is

connected to a Remote Processor wait pin it is no longer

waited and can now terminate its read cycle This state be-

gins the Termination Phase The action specified in the con-

ditional box is only executed while RAE REM-RD is assert-

eda clock edge is not necessary In all RSE states except

RSE4 (DMEM) LCL will fall a propagation delay after

RAE REM-RD is deasserted In RSE4 LCL remains high

through the whole state

On the CPU-CLK after RAE REM-RD is deasserted RASM

enters RSF1 from every RSE state except RSE4 (DMEM) In

RSF1 LCL remains low and A remains in TRI-STATE while

CPU-CLK is high (ie for the first half T-state of RSF1)

From RSE4 RASM enters RSF2 on the CPU-CLK after

RAE REM-RD is deasserted In RSF2 LCL remains high

while both A and AD remain in TRI-STATE

From RSF1 the next clock will return the state machine

back to state RSA1 where it will loop until another Remote

Access is initiated If the access was to IMEM then the last

action of the remote access before returning to RSA is to

switch HIB and increment the PC if the high byte was read

From RSF2 the next CPU-CLK returns to state RSA3 where

LCL returns low but A and AD remain TRI-STATE for the

first half T-state of RSA3 If no Remote Access is initiated

the next state will be RSA1 where it will loop until another

Remote Access is initiated

The example in

Figure 4-15 shows the BCP executing the

first of two consecutive Data Memory reads when REM-RD

goes low In response XACK goes low waiting the remote

processor At the end of the first instruction although the

BCP begins its second read by taking ALE high the RASM

now takes control of the bus and takes LCL high at the end

of T1 A one T-state delay is built into this transfer to ensure

that READ has been deasserted before the data bus is

switched The Timing Control Unit is now waited inserting

remote access wait states TWr as RASM takes over

The remote address is permitted one T-state to settle on the

BCP address bus before READ goes low XACK then re-

turns high one T-state plus the programmed Data Memory

wait state TWd later having satisfied the memory access

time The Remote Processor will respond by deasserting

REM-RD high to which the BCP in turn responds by deas-

serting READ high Following READ being deasserted high

the BCP waits till the end of the next T-state before taking

LCL low again ensuring that the read cycle has concluded

before the bus is switched Control is then returned to the

Timing Control Unit and the local memory read continues

422 Latched Read

This mode differs from the Buffered Read mode in the way

the access is terminated A latched Read cycle ends after

the data being read is valid and the termination doesn’t wait

for the trailing edge of REM-RD Therefore the Arbitration

and Access Phases of the Latched Read mode are the

same as for the Buffered Read mode The complete flow

chart for the Latched Read mode is shown in

Figure 4-16

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